From mboxrd@z Thu Jan 1 00:00:00 1970 Subject: Re: [LINUX PATCH v2 1/3] spi: Added dummy_cycle entry in the spi_transfer structure. To: Mark Brown References: <1460039969-9835-1-git-send-email-lakshmis@xilinx.com> <57067694.8030806@atmel.com> <4FF8F58FAA9D5D4193D4E554E4352C5902C720DE@XAP-PVEXMBX02.xlnx.xilinx.com> <570F4F9F.3090605@atmel.com> <20160414085707.GE18024@sirena.org.uk> From: Cyrille Pitchen CC: Lakshmi Sai Krishna Potthuri , Michal Simek , Soren Brinkmann , "David Woodhouse" , Brian Norris , Javier Martinez Canillas , Boris Brezillon , Stephen Warren , Geert Uytterhoeven , "Andrew F. Davis" , Marek Vasut , Jagan Teki , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , "linux-mtd@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "linux-spi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Harini Katakam , Punnaiah Choudary Kalluri , Anirudha Sarangi , "R, Vignesh" Message-ID: <570FB5D8.90807@atmel.com> Date: Thu, 14 Apr 2016 17:23:04 +0200 MIME-Version: 1.0 In-Reply-To: <20160414085707.GE18024@sirena.org.uk> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Le 14/04/2016 10:57, Mark Brown a écrit : > On Thu, Apr 14, 2016 at 10:06:55AM +0200, Cyrille Pitchen wrote: > >> I understand but you propose to patch both the SPI layer and the m25p80 driver >> to introduce some support which is already provided by the "spi_flash_read" >> hook: struct spi_flash_read_message has already a "dummy_bytes" field. >> IMHO, it looks redundant. > > My understanding is that this is intended for dummy bits rather than > dummy bytes. > dummy_bits == (dummy_bytes * 8) and dummy_cycles == ((dummy_bytes * 8) / addr_nbits) witch addr_nbits in {1, 2, 4} the struct_flash_read_message has both dummy_bytes and addr_nbits members. The spi-nor framework seems to always provide a multiple of 8 for dummy *bits*. I guess because the m25p80 driver only supports such number of dummy bits but also because all SPI memories can be configured so their number of dummy cycles keeps the byte alignment for the data to follow. It still allows to use less than 8 dummy *cycles*, for instance the factory settings for Macronix Quad SPI memories are: - 4 dummy cycles for Fast Read 1-2-2 (hence 8 dummy bits) - 6 dummy cycles for Fast Read x-4-4 (hence 24 dummy bits) AFAIK, only Micron QSPI memories could be configured so the number of dummy cycles doesn't result in a multiple of 8 bits but theirs are not the recommanded timings provided by the datasheet. Micron factory settings are: - 10 dummy cycles for Fast Read x-4-4 (hence 40 dummy bits) - 8 dummy cycles for other Fast Reads. Best regards, Cyrille From mboxrd@z Thu Jan 1 00:00:00 1970 From: Cyrille Pitchen Subject: Re: [LINUX PATCH v2 1/3] spi: Added dummy_cycle entry in the spi_transfer structure. Date: Thu, 14 Apr 2016 17:23:04 +0200 Message-ID: <570FB5D8.90807@atmel.com> References: <1460039969-9835-1-git-send-email-lakshmis@xilinx.com> <57067694.8030806@atmel.com> <4FF8F58FAA9D5D4193D4E554E4352C5902C720DE@XAP-PVEXMBX02.xlnx.xilinx.com> <570F4F9F.3090605@atmel.com> <20160414085707.GE18024@sirena.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: Lakshmi Sai Krishna Potthuri , Michal Simek , Soren Brinkmann , "David Woodhouse" , Brian Norris , Javier Martinez Canillas , Boris Brezillon , Stephen Warren , Geert Uytterhoeven , "Andrew F. Davis" , Marek Vasut , Jagan Teki , =?UTF-8?B?UmFmYcWCIE1pxYJlY2tp?= , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , Harini Katakam , Punnaiah C To: Mark Brown Return-path: In-Reply-To: <20160414085707.GE18024-GFdadSzt00ze9xe1eoZjHA@public.gmane.org> Sender: linux-spi-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-ID: Le 14/04/2016 10:57, Mark Brown a =E9crit : > On Thu, Apr 14, 2016 at 10:06:55AM +0200, Cyrille Pitchen wrote: >=20 >> I understand but you propose to patch both the SPI layer and the m25= p80 driver >> to introduce some support which is already provided by the "spi_flas= h_read" >> hook: struct spi_flash_read_message has already a "dummy_bytes" fiel= d. >> IMHO, it looks redundant. >=20 > My understanding is that this is intended for dummy bits rather than > dummy bytes. >=20 dummy_bits =3D=3D (dummy_bytes * 8) and dummy_cycles =3D=3D ((dummy_bytes * 8) / addr_nbits) witch addr_nbits in {1, 2, 4} the struct_flash_read_message has both dummy_bytes and addr_nbits membe= rs. The spi-nor framework seems to always provide a multiple of 8 for dummy= *bits*. I guess because the m25p80 driver only supports such number of dummy bi= ts but also because all SPI memories can be configured so their number of dumm= y cycles keeps the byte alignment for the data to follow. It still allows to use less than 8 dummy *cycles*, for instance the fac= tory settings for Macronix Quad SPI memories are: - 4 dummy cycles for Fast Read 1-2-2 (hence 8 dummy bits) - 6 dummy cycles for Fast Read x-4-4 (hence 24 dummy bits) AFAIK, only Micron QSPI memories could be configured so the number of d= ummy cycles doesn't result in a multiple of 8 bits but theirs are not the recommanded timings provided by the datasheet. Micron factory settings are: - 10 dummy cycles for Fast Read x-4-4 (hence 40 dummy bits) - 8 dummy cycles for other Fast Reads. Best regards, Cyrille -- To unsubscribe from this list: send the line "unsubscribe linux-spi" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: cyrille.pitchen@atmel.com (Cyrille Pitchen) Date: Thu, 14 Apr 2016 17:23:04 +0200 Subject: [LINUX PATCH v2 1/3] spi: Added dummy_cycle entry in the spi_transfer structure. In-Reply-To: <20160414085707.GE18024@sirena.org.uk> References: <1460039969-9835-1-git-send-email-lakshmis@xilinx.com> <57067694.8030806@atmel.com> <4FF8F58FAA9D5D4193D4E554E4352C5902C720DE@XAP-PVEXMBX02.xlnx.xilinx.com> <570F4F9F.3090605@atmel.com> <20160414085707.GE18024@sirena.org.uk> Message-ID: <570FB5D8.90807@atmel.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Le 14/04/2016 10:57, Mark Brown a ?crit : > On Thu, Apr 14, 2016 at 10:06:55AM +0200, Cyrille Pitchen wrote: > >> I understand but you propose to patch both the SPI layer and the m25p80 driver >> to introduce some support which is already provided by the "spi_flash_read" >> hook: struct spi_flash_read_message has already a "dummy_bytes" field. >> IMHO, it looks redundant. > > My understanding is that this is intended for dummy bits rather than > dummy bytes. > dummy_bits == (dummy_bytes * 8) and dummy_cycles == ((dummy_bytes * 8) / addr_nbits) witch addr_nbits in {1, 2, 4} the struct_flash_read_message has both dummy_bytes and addr_nbits members. The spi-nor framework seems to always provide a multiple of 8 for dummy *bits*. I guess because the m25p80 driver only supports such number of dummy bits but also because all SPI memories can be configured so their number of dummy cycles keeps the byte alignment for the data to follow. It still allows to use less than 8 dummy *cycles*, for instance the factory settings for Macronix Quad SPI memories are: - 4 dummy cycles for Fast Read 1-2-2 (hence 8 dummy bits) - 6 dummy cycles for Fast Read x-4-4 (hence 24 dummy bits) AFAIK, only Micron QSPI memories could be configured so the number of dummy cycles doesn't result in a multiple of 8 bits but theirs are not the recommanded timings provided by the datasheet. Micron factory settings are: - 10 dummy cycles for Fast Read x-4-4 (hence 40 dummy bits) - 8 dummy cycles for other Fast Reads. Best regards, Cyrille