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From: Akira Yokosawa <akiyks@gmail.com>
To: paulmck@linux.vnet.ibm.com
Cc: perfbook@vger.kernel.org, Akira Yokosawa <akiyks@gmail.com>
Subject: [PATCH 3/3] advsync: Tweak vertical spacing around code snippets
Date: Sat, 16 Apr 2016 17:17:00 +0900	[thread overview]
Message-ID: <5711F4FC.4070000@gmail.com> (raw)
In-Reply-To: <5711F2CF.1030907@gmail.com>

From e9f9f2126a24841bb19970292716819f0300872b Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@gmail.com>
Date: Sat, 16 Apr 2016 12:50:54 +0900
Subject: [PATCH 3/3] advsync: Tweak vertical spacing around code snippets

In the `Guarantees` subsection, code snippets have wider
vertical spacings around them than other code snippets in the
section.
This is supposedly caused by the interaction between the
'enumerate' tag and the 'minipage' tag.
This commit removes \vspace{} commands around minipages within
enumerations. Some \vspace{} commands which break sentences
are reduced in width and moved into minipages to stabilize the
resulting vertical spacings.

Signed-off-by: Akira Yokosawa <akiyks@gmail.com>
---
 advsync/memorybarriers.tex | 32 +++-----------------------------
 1 file changed, 3 insertions(+), 29 deletions(-)

diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 0ef020f..505adc0 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1236,72 +1236,61 @@ There are some minimal guarantees that may be expected of a CPU:
 \item	On any given CPU, dependent memory accesses will be issued in order,
 	with respect to itself.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = P; D = *Q;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will issue the following memory operations:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 Q = LOAD P, D = LOAD *Q
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	and always in that order.

 \item	Overlapping loads and stores within a particular CPU will appear to be
 	ordered within that CPU.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = *X; *X = b;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will only issue the following sequence of memory operations:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 a = LOAD *X, STORE *X = b
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	And for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *X = c; d = *X;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	the CPU will only issue:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 STORE *X = c, d = LOAD *X
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	(Loads and stores overlap if they are targeted at overlapping pieces of
 	memory).
@@ -1317,19 +1306,15 @@ And there are a number of things that \emph{must} or \emph{must not} be assumed:
 \item	It \emph{must not} be assumed that independent loads and stores will
 	be issued in the order given.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *B; *D = Z;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any of the following sequences:

-
-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1341,23 +1326,19 @@ STORE *D = Z,  X = LOAD *A,  Y = LOAD *B
 STORE *D = Z,  Y = LOAD *B,  X = LOAD *A
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 \item	It \emph{must} be assumed that overlapping memory accesses may
 	be merged or discarded.  This means that for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 X = *A; Y = *(A + 4);
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any one of the following sequences:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1365,23 +1346,20 @@ X = LOAD *A; Y = LOAD *(A + 4);
 Y = LOAD *(A + 4); X = LOAD *A;
 {X, Y} = LOAD {*A, *(A + 4) };
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	And for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *(A + 4) = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get any of:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1389,23 +1367,20 @@ STORE *A = X; STORE *(A + 4) = Y;
 STORE *(A + 4) = Y; STORE *A = X;
 STORE {*A, *(A + 4) } = {X, Y};
 \end{verbatim}
+\vspace{1pt}
 \end{minipage}
-\vspace{5pt}

 	Finally, for:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
 *A = X; *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 	we may get either of:

-\vspace{5pt}
 \begin{minipage}[t]{\columnwidth}
 \scriptsize
 \begin{verbatim}
@@ -1413,7 +1388,6 @@ STORE *A = X; STORE *A = Y;
 STORE *A = Y;
 \end{verbatim}
 \end{minipage}
-\vspace{5pt}

 \end{enumerate}

-- 
1.9.1



  parent reply	other threads:[~2016-04-16  8:17 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-16  8:07 [PATCH 0/3] advsync: Typo fix and vertical spacing tweaks Akira Yokosawa
2016-04-16  8:11 ` [PATCH 1/3] advsync: Fix a trivial typo Akira Yokosawa
2016-04-16  8:14 ` [PATCH 2/3] advsync: Add necessary blank lines around minipages Akira Yokosawa
2016-04-16  8:17 ` Akira Yokosawa [this message]
2016-04-17  3:36 ` [PATCH 0/3] advsync: Typo fix and vertical spacing tweaks Paul E. McKenney

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