From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1arcU1-0005ed-L3 for qemu-devel@nongnu.org; Sat, 16 Apr 2016 22:30:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1arcTy-0005nf-CC for qemu-devel@nongnu.org; Sat, 16 Apr 2016 22:30:45 -0400 Received: from mout.web.de ([212.227.15.14]:64418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1arcTy-0005nb-3N for qemu-devel@nongnu.org; Sat, 16 Apr 2016 22:30:42 -0400 References: <1460691099-3024-1-git-send-email-peterx@redhat.com> <1460691099-3024-3-git-send-email-peterx@redhat.com> From: Jan Kiszka Message-ID: <5712F541.60703@web.de> Date: Sat, 16 Apr 2016 19:30:25 -0700 MIME-Version: 1.0 In-Reply-To: <1460691099-3024-3-git-send-email-peterx@redhat.com> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 02/13] intel_iommu: set IR bit for ECAP register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu , qemu-devel@nongnu.org Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On 2016-04-14 20:31, Peter Xu wrote: > Enable IR in IOMMU Extended Capability register. > > Signed-off-by: Peter Xu > --- > hw/i386/intel_iommu.c | 7 +++++++ > hw/i386/intel_iommu_internal.h | 2 ++ > 2 files changed, 9 insertions(+) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 4b0558e..17668d6 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -24,6 +24,7 @@ > #include "exec/address-spaces.h" > #include "intel_iommu_internal.h" > #include "hw/pci/pci.h" > +#include "hw/boards.h" > > /*#define DEBUG_INTEL_IOMMU*/ > #ifdef DEBUG_INTEL_IOMMU > @@ -1941,6 +1942,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) > */ > static void vtd_init(IntelIOMMUState *s) > { > + MachineState *ms = MACHINE(qdev_get_machine()); > + > memset(s->csr, 0, DMAR_REG_SIZE); > memset(s->wmask, 0, DMAR_REG_SIZE); > memset(s->w1cmask, 0, DMAR_REG_SIZE); > @@ -1961,6 +1964,10 @@ static void vtd_init(IntelIOMMUState *s) > VTD_CAP_SAGAW | VTD_CAP_MAMV | VTD_CAP_PSI | VTD_CAP_SLLPS; > s->ecap = VTD_ECAP_QI | VTD_ECAP_IRO; > > + if (ms->iommu_intr) { This cannot work, the field doesn't exit yet. Please test bisectability after reordering patches. Jan > + s->ecap |= VTD_ECAP_IR; > + } > + > vtd_reset_context_cache(s); > vtd_reset_iotlb(s); > > diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h > index b648e69..5b98a11 100644 > --- a/hw/i386/intel_iommu_internal.h > +++ b/hw/i386/intel_iommu_internal.h > @@ -176,6 +176,8 @@ > /* (offset >> 4) << 8 */ > #define VTD_ECAP_IRO (DMAR_IOTLB_REG_OFFSET << 4) > #define VTD_ECAP_QI (1ULL << 1) > +/* Interrupt Remapping support */ > +#define VTD_ECAP_IR (1ULL << 3) > > /* CAP_REG */ > /* (offset >> 4) << 24 */ >