From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:41210) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1asqXg-0003iK-8y for qemu-devel@nongnu.org; Wed, 20 Apr 2016 07:43:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1asqXc-0002aU-98 for qemu-devel@nongnu.org; Wed, 20 Apr 2016 07:43:36 -0400 Received: from mail-lf0-x235.google.com ([2a00:1450:4010:c07::235]:33496) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1asqXc-0002aQ-1X for qemu-devel@nongnu.org; Wed, 20 Apr 2016 07:43:32 -0400 Received: by mail-lf0-x235.google.com with SMTP id e190so39135369lfe.0 for ; Wed, 20 Apr 2016 04:43:31 -0700 (PDT) References: <1460044433-19282-1-git-send-email-sergey.fedorov@linaro.org> <1460044433-19282-6-git-send-email-sergey.fedorov@linaro.org> <87potkvc2h.fsf@linaro.org> From: Sergey Fedorov Message-ID: <57176B61.5060000@gmail.com> Date: Wed, 20 Apr 2016 14:43:29 +0300 MIME-Version: 1.0 In-Reply-To: <87potkvc2h.fsf@linaro.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 05/11] tcg/i386: Make direct jump patching thread-safe List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , Sergey Fedorov Cc: qemu-devel@nongnu.org, Paolo Bonzini , Peter Crosthwaite , Richard Henderson On 20/04/16 12:55, Alex Bennée wrote: > Sergey Fedorov writes: >> diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c >> index 9187d34caf6d..3ffb7b3124d8 100644 >> --- a/tcg/i386/tcg-target.inc.c >> +++ b/tcg/i386/tcg-target.inc.c >> @@ -1123,6 +1123,19 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) >> tcg_out_branch(s, 0, dest); >> } >> >> +static void tcg_out_nopn(TCGContext *s, int n) >> +{ >> + static const uint8_t nop1[] = { 0x90 }; >> + static const uint8_t nop2[] = { 0x66, 0x90 }; >> + static const uint8_t nop3[] = { 0x8d, 0x76, 0x00 }; >> + static const uint8_t *const nopn[] = { nop1, nop2, nop3 }; >> + int i; >> + assert(n <= ARRAY_SIZE(nopn)); >> + for (i = 0; i < n; ++i) { >> + tcg_out8(s, nopn[n - 1][i]); >> + } >> +} > *shudder* I recall x86 instruction encoding is weird. Maybe a comment > for the function to describe the 3 forms of NOP we have here? Okay. > >> + >> #if defined(CONFIG_SOFTMMU) >> /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, >> * int mmu_idx, uintptr_t ra) >> @@ -1777,6 +1790,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, >> case INDEX_op_goto_tb: >> if (s->tb_jmp_offset) { >> /* direct jump method */ >> + /* align jump displacement for atomic pathing */ > s/pathing/patching/ Nice catch, thanks :) Kind regards, Sergey