From: Balbir Singh <bsingharora@gmail.com>
To: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com>,
benh@kernel.crashing.org, paulus@samba.org, mpe@ellerman.id.au
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH V2 41/68] powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code
Date: Fri, 22 Apr 2016 17:32:49 +1000 [thread overview]
Message-ID: <5719D3A1.8070008@gmail.com> (raw)
In-Reply-To: <1460182444-2468-42-git-send-email-aneesh.kumar@linux.vnet.ibm.com>
On 09/04/16 16:13, Aneesh Kumar K.V wrote:
> We also use MMU_FTR_RADIX to branch out from code path specific to
> hash.
>
> No functionality change.
>
> Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
> ---
> arch/powerpc/kernel/entry_64.S | 7 +++++--
> arch/powerpc/kernel/exceptions-64s.S | 28 +++++++++++++++++++++++-----
> arch/powerpc/kernel/machine_kexec_64.c | 6 ++++--
> arch/powerpc/kernel/mce_power.c | 10 ++++++++++
> arch/powerpc/kernel/process.c | 15 +++++++++------
> arch/powerpc/xmon/xmon.c | 2 +-
> 6 files changed, 52 insertions(+), 16 deletions(-)
>
> diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
> index 9916d150b28c..8b9d68676d2b 100644
> --- a/arch/powerpc/kernel/entry_64.S
> +++ b/arch/powerpc/kernel/entry_64.S
> @@ -519,7 +519,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_STCX_CHECKS_ADDRESS)
> std r6,PACACURRENT(r13) /* Set new 'current' */
>
> ld r8,KSP(r4) /* new stack pointer */
> -#ifdef CONFIG_PPC_BOOK3S
> +#ifdef CONFIG_PPC_STD_MMU_64
> +BEGIN_MMU_FTR_SECTION
> + b 2f
> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
> BEGIN_FTR_SECTION
> clrrdi r6,r8,28 /* get its ESID */
> clrrdi r9,r1,28 /* get current sp ESID */
> @@ -565,7 +568,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
> slbmte r7,r0
> isync
> 2:
> -#endif /* !CONFIG_PPC_BOOK3S */
> +#endif /* CONFIG_PPC_STD_MMU_64 */
>
> CURRENT_THREAD_INFO(r7, r8) /* base of new stack */
> /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index 7716cebf4b8e..d2afec81d04d 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -983,7 +983,13 @@ data_access_common:
> ld r3,PACA_EXGEN+EX_DAR(r13)
> lwz r4,PACA_EXGEN+EX_DSISR(r13)
> li r5,0x300
> + std r3,_DAR(r1)
> + std r4,_DSISR(r1)
> +BEGIN_MMU_FTR_SECTION
> b do_hash_page /* Try to handle as hpte fault */
> +MMU_FTR_SECTION_ELSE
> + b handle_page_fault
Normal kernel page fault handler?
> +ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
>
> .align 7
> .globl h_data_storage_common
> @@ -1008,7 +1014,13 @@ instruction_access_common:
> ld r3,_NIP(r1)
> andis. r4,r12,0x5820
> li r5,0x400
> + std r3,_DAR(r1)
> + std r4,_DSISR(r1)
> +BEGIN_MMU_FTR_SECTION
> b do_hash_page /* Try to handle as hpte fault */
> +MMU_FTR_SECTION_ELSE
> + b handle_page_fault
> +ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)
>
> STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception)
>
> @@ -1476,8 +1488,11 @@ slb_miss_realmode:
> stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
> std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
>
> +#ifdef CONFIG_PPC_STD_MMU_64
> +BEGIN_MMU_FTR_SECTION
> bl slb_allocate_realmode
> -
> +END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX)
> +#endif
> /* All done -- return from exception. */
>
> ld r10,PACA_EXSLB+EX_LR(r13)
> @@ -1485,7 +1500,9 @@ slb_miss_realmode:
> lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
>
> mtlr r10
> -
> +BEGIN_MMU_FTR_SECTION
> + b 2f
> +END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)
> andi. r10,r12,MSR_RI /* check for unrecoverable exception */
> beq- 2f
>
> @@ -1536,9 +1553,7 @@ power4_fixup_nap:
> */
> .align 7
> do_hash_page:
> - std r3,_DAR(r1)
> - std r4,_DSISR(r1)
> -
> +#ifdef CONFIG_PPC_STD_MMU_64
> andis. r0,r4,0xa410 /* weird error? */
> bne- handle_page_fault /* if not, try to insert a HPTE */
> andis. r0,r4,DSISR_DABRMATCH@h
> @@ -1566,6 +1581,7 @@ do_hash_page:
>
> /* Error */
> blt- 13f
> +#endif /* CONFIG_PPC_STD_MMU_64 */
>
> /* Here we have a page fault that hash_page can't handle. */
> handle_page_fault:
> @@ -1592,6 +1608,7 @@ handle_dabr_fault:
> 12: b ret_from_except_lite
>
>
> +#ifdef CONFIG_PPC_STD_MMU_64
> /* We have a page fault that hash_page could handle but HV refused
> * the PTE insertion
> */
> @@ -1601,6 +1618,7 @@ handle_dabr_fault:
> ld r4,_DAR(r1)
> bl low_hash_fault
> b ret_from_except
> +#endif
>
> /*
> * We come here as a result of a DSI at a point where we don't want
> diff --git a/arch/powerpc/kernel/machine_kexec_64.c b/arch/powerpc/kernel/machine_kexec_64.c
> index 0fbd75d185d7..1da864c00db0 100644
> --- a/arch/powerpc/kernel/machine_kexec_64.c
> +++ b/arch/powerpc/kernel/machine_kexec_64.c
> @@ -76,6 +76,7 @@ int default_machine_kexec_prepare(struct kimage *image)
> * end of the blocked region (begin >= high). Use the
> * boolean identity !(a || b) === (!a && !b).
> */
> +#ifdef CONFIG_PPC_STD_MMU_64
> if (htab_address) {
> low = __pa(htab_address);
> high = low + htab_size_bytes;
> @@ -88,6 +89,7 @@ int default_machine_kexec_prepare(struct kimage *image)
> return -ETXTBSY;
> }
> }
> +#endif /* CONFIG_PPC_STD_MMU_64 */
>
> /* We also should not overwrite the tce tables */
> for_each_node_by_type(node, "pci") {
> @@ -381,7 +383,7 @@ void default_machine_kexec(struct kimage *image)
> /* NOTREACHED */
> }
>
> -#ifndef CONFIG_PPC_BOOK3E
> +#ifdef CONFIG_PPC_STD_MMU_64
> /* Values we need to export to the second kernel via the device tree. */
> static unsigned long htab_base;
> static unsigned long htab_size;
> @@ -428,4 +430,4 @@ static int __init export_htab_values(void)
> return 0;
> }
> late_initcall(export_htab_values);
> -#endif /* !CONFIG_PPC_BOOK3E */
> +#endif /* CONFIG_PPC_STD_MMU_64 */
> diff --git a/arch/powerpc/kernel/mce_power.c b/arch/powerpc/kernel/mce_power.c
> index ee62b197502d..92a66a2a9b85 100644
> --- a/arch/powerpc/kernel/mce_power.c
> +++ b/arch/powerpc/kernel/mce_power.c
> @@ -77,6 +77,7 @@ void __flush_tlb_power9(unsigned int action)
>
>
> /* flush SLBs and reload */
> +#ifdef CONFIG_PPC_MMU_STD_64
> static void flush_and_reload_slb(void)
> {
> struct slb_shadow *slb;
> @@ -110,6 +111,7 @@ static void flush_and_reload_slb(void)
> asm volatile("slbmte %0,%1" : : "r" (rs), "r" (rb));
> }
> }
> +#endif
>
> static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
> {
> @@ -120,6 +122,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
> * reset the error bits whenever we handle them so that at the end
> * we can check whether we handled all of them or not.
> * */
> +#ifdef CONFIG_PPC_MMU_STD_64
> if (dsisr & slb_error_bits) {
> flush_and_reload_slb();
> /* reset error bits */
> @@ -131,6 +134,7 @@ static long mce_handle_derror(uint64_t dsisr, uint64_t slb_error_bits)
> /* reset error bits */
> dsisr &= ~P7_DSISR_MC_TLB_MULTIHIT_MFTLB;
> }
> +#endif
> /* Any other errors we don't understand? */
> if (dsisr & 0xffffffffUL)
> handled = 0;
> @@ -150,6 +154,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
> switch (P7_SRR1_MC_IFETCH(srr1)) {
> case 0:
> break;
> +#ifdef CONFIG_PPC_MMU_STD_64
> case P7_SRR1_MC_IFETCH_SLB_PARITY:
> case P7_SRR1_MC_IFETCH_SLB_MULTIHIT:
> /* flush and reload SLBs for SLB errors. */
> @@ -162,6 +167,7 @@ static long mce_handle_common_ierror(uint64_t srr1)
> handled = 1;
> }
> break;
> +#endif
> default:
> break;
> }
> @@ -175,10 +181,12 @@ static long mce_handle_ierror_p7(uint64_t srr1)
>
> handled = mce_handle_common_ierror(srr1);
>
> +#ifdef CONFIG_PPC_MMU_STD_64
> if (P7_SRR1_MC_IFETCH(srr1) == P7_SRR1_MC_IFETCH_SLB_BOTH) {
> flush_and_reload_slb();
> handled = 1;
> }
> +#endif
> return handled;
> }
>
> @@ -321,10 +329,12 @@ static long mce_handle_ierror_p8(uint64_t srr1)
>
> handled = mce_handle_common_ierror(srr1);
>
> +#ifdef CONFIG_PPC_MMU_STD_64
> if (P7_SRR1_MC_IFETCH(srr1) == P8_SRR1_MC_IFETCH_ERAT_MULTIHIT) {
> flush_and_reload_slb();
> handled = 1;
> }
> +#endif
> return handled;
> }
>
> diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
> index d7a9df51b974..e35b018be765 100644
> --- a/arch/powerpc/kernel/process.c
> +++ b/arch/powerpc/kernel/process.c
> @@ -1075,7 +1075,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
> }
> #endif /* CONFIG_PPC64 */
>
> -#ifdef CONFIG_PPC_BOOK3S_64
> +#ifdef CONFIG_PPC_STD_MMU_64
> batch = this_cpu_ptr(&ppc64_tlb_batch);
> if (batch->active) {
> current_thread_info()->local_flags |= _TLF_LAZY_MMU;
> @@ -1083,7 +1083,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
> __flush_tlb_pending(batch);
> batch->active = 0;
> }
> -#endif /* CONFIG_PPC_BOOK3S_64 */
> +#endif /* CONFIG_PPC_STD_MMU_64 */
>
> #ifdef CONFIG_PPC_ADV_DEBUG_REGS
> switch_booke_debug_regs(&new->thread.debug);
> @@ -1129,7 +1129,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
>
> last = _switch(old_thread, new_thread);
>
> -#ifdef CONFIG_PPC_BOOK3S_64
> +#ifdef CONFIG_PPC_STD_MMU_64
> if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
> current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
> batch = this_cpu_ptr(&ppc64_tlb_batch);
> @@ -1138,8 +1138,7 @@ struct task_struct *__switch_to(struct task_struct *prev,
>
> if (current_thread_info()->task->thread.regs)
> restore_math(current_thread_info()->task->thread.regs);
> -
> -#endif /* CONFIG_PPC_BOOK3S_64 */
> +#endif /* CONFIG_PPC_STD_MMU_64 */
>
> return last;
> }
> @@ -1374,6 +1373,9 @@ static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
> unsigned long sp_vsid;
> unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
>
> + if (radix_enabled())
> + return;
> +
> if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
> sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
> << SLB_VSID_SHIFT_1T;
> @@ -1920,7 +1922,8 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
> * the heap, we can put it above 1TB so it is backed by a 1TB
> * segment. Otherwise the heap will be in the bottom 1TB
> * which always uses 256MB segments and this may result in a
> - * performance penalty.
> + * performance penalty. We don't need to worry about radix. For
> + * radix, mmu_highuser_ssize remains unchanged from 256MB.
> */
> if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
> base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
> diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c
> index 942796fa4767..308283b7b60c 100644
> --- a/arch/powerpc/xmon/xmon.c
> +++ b/arch/powerpc/xmon/xmon.c
> @@ -2913,7 +2913,7 @@ static void xmon_print_symbol(unsigned long address, const char *mid,
> printf("%s", after);
> }
>
> -#ifdef CONFIG_PPC_BOOK3S_64
> +#ifdef CONFIG_PPC_STD_MMU_64
> void dump_segments(void)
> {
> int i;
>
next prev parent reply other threads:[~2016-04-22 7:32 UTC|newest]
Thread overview: 139+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-09 6:12 [PATCH V2 00/68] PowerISA 3.0 Radix page table support Aneesh Kumar K.V
2016-04-09 6:12 ` [PATCH V2 01/68] powerpc/cxl: Use REGION_ID instead of opencoding Aneesh Kumar K.V
2016-04-11 0:37 ` Andrew Donnellan
2016-04-13 2:42 ` Aneesh Kumar K.V
2016-04-20 3:03 ` Michael Ellerman
2016-04-20 7:53 ` Aneesh Kumar K.V
2016-04-09 6:12 ` [PATCH V2 02/68] powerpc/mm/nohash: Return correctly from flush_tlb_page Aneesh Kumar K.V
2016-04-20 4:08 ` [V2, " Michael Ellerman
2016-04-20 7:49 ` Aneesh Kumar K.V
2016-04-09 6:12 ` [PATCH V2 03/68] powerpc/mm/nohash: Update non SMP version of flush_tlb_page to handle hugetlb address Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 04/68] powerpc/mm: Use big endian page table for book3s 64 Aneesh Kumar K.V
2016-04-22 11:01 ` Michael Ellerman
2016-04-24 22:29 ` Aneesh Kumar K.V
2016-05-29 11:03 ` Anton Blanchard
2016-05-29 21:27 ` Benjamin Herrenschmidt
2016-05-29 23:08 ` Anton Blanchard
2016-05-30 3:42 ` Michael Ellerman
2016-05-30 5:31 ` Anton Blanchard
2016-05-30 8:42 ` Aneesh Kumar K.V
2016-05-30 11:00 ` Benjamin Herrenschmidt
2016-05-30 14:48 ` Aneesh Kumar K.V
2016-05-30 14:59 ` Segher Boessenkool
2016-04-09 6:13 ` [PATCH V2 05/68] powerpc/mm: use _PAGE_READ to indicate Read access Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 06/68] powerpc/mm/subpage: Clear RWX bit to indicate no access Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 07/68] powerpc/mm: Use pte_user instead of opencoding Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 08/68] powerpc/mm: Replace _PAGE_USER with _PAGE_PRIVILEGED Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 09/68] powerpc/mm: Remove RPN_SHIFT and RPN_SIZE Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 10/68] powerpc/mm: Update _PAGE_KERNEL_RO Aneesh Kumar K.V
2016-11-20 0:43 ` [V2,10/68] " Geoff Levand
2016-11-20 18:03 ` Aneesh Kumar K.V
2016-11-21 0:33 ` Geoff Levand
2016-11-23 10:41 ` Aneesh Kumar K.V
2016-11-24 4:04 ` Geoff Levand
2016-04-09 6:13 ` [PATCH V2 11/68] powerpc/mm: Use helper for finding pte bits mapping I/O area Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 12/68] powerpc/mm: Drop WIMG in favour of new constants Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 13/68] powerpc/mm: Use generic version of pmdp_clear_flush_young Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 14/68] powerpc/mm: Use generic version of ptep_clear_flush_young Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 15/68] powerpc/mm: Move common data structure between radix and hash to book3s 64 generic headers Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 16/68] powerpc/mm/power9: Add partition table format Aneesh Kumar K.V
2016-04-11 0:59 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 17/68] powerpc/mm/hash: Add support for POWER9 hash Aneesh Kumar K.V
2016-04-11 4:55 ` Balbir Singh
2016-04-16 19:06 ` Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 18/68] powerpc/mm: Move hash and no hash code to separate files Aneesh Kumar K.V
2016-04-11 5:14 ` Balbir Singh
2016-04-17 10:20 ` Aneesh Kumar K.V
2016-04-20 6:17 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 19/68] powerpc/mm/book3s: Rename hash specific PTE bits to carry H_ prefix Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 20/68] powerpc/mm: Handle _PTE_NONE_MASK Aneesh Kumar K.V
2016-04-11 6:09 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 21/68] powerpc/mm: Move common pte bits and accessors to book3s/64/pgtable.h Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 22/68] powerpc/mm: Move pte accessors that operate on common pte bits to pgtable.h Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 23/68] powerpc/mm: Make page table size a variable Aneesh Kumar K.V
2016-04-12 1:49 ` Balbir Singh
2016-04-17 10:27 ` Aneesh Kumar K.V
2016-04-20 6:21 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 24/68] powerpc/mm: Move page table index and and vaddr to pgtable.h Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 25/68] powerpc/mm: Move pte related function together Aneesh Kumar K.V
2016-04-14 6:50 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 26/68] powerpc/mm/radix: Add radix pte defines Aneesh Kumar K.V
2016-04-21 4:12 ` Balbir Singh
2016-04-23 8:30 ` Benjamin Herrenschmidt
2016-04-26 1:40 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 27/68] powerpc/mm/radix: Dummy radix_enabled() Aneesh Kumar K.V
2016-04-21 4:27 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 28/68] powerpc/mm: Add radix callbacks to pte accessors Aneesh Kumar K.V
2016-04-21 4:30 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 29/68] powerpc/mm: Move hugetlb and THP related pmd accessors to pgtable.h Aneesh Kumar K.V
2016-04-21 9:53 ` Balbir Singh
2016-04-21 9:59 ` Michael Ellerman
2016-04-21 11:42 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 30/68] powerpc/mm/radix: Add radix callback for pmd accessors Aneesh Kumar K.V
2016-04-21 11:39 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 31/68] powerpc/mm: Abstraction for early init routines Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 32/68] powerpc/mm/radix: Add radix callback " Aneesh Kumar K.V
2016-04-21 12:22 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 33/68] powerpc/mm: Abstraction for vmemmap and map_kernel_page Aneesh Kumar K.V
2016-04-21 12:59 ` Balbir Singh
2016-04-28 6:17 ` Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 34/68] powerpc/mm/radix: Add radix callback for vmemmap and map_kernel page Aneesh Kumar K.V
2016-04-21 13:46 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 35/68] powerpc/mm: Abstraction for switch_mmu_context Aneesh Kumar K.V
2016-04-21 14:12 ` Balbir Singh
2016-04-28 6:13 ` Aneesh Kumar K.V
2016-04-28 6:13 ` Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 36/68] powerpc/mm/radix: Add mmu context handling callback for radix Aneesh Kumar K.V
2016-04-22 6:19 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 37/68] powerpc/mm: Rename mmu_context_hash64.c to mmu_context_book3s64.c Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 38/68] powerpc/mm: Hash linux abstraction for tlbflush routines Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 39/68] powerpc/mm/radix: Add " Aneesh Kumar K.V
2016-04-22 7:20 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 40/68] powerpc/mm/radix: Add MMU_FTR_RADIX Aneesh Kumar K.V
2016-04-22 7:23 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 41/68] powerpc/mm/radix: Use STD_MMU_64 to properly isolate hash related code Aneesh Kumar K.V
2016-04-22 7:32 ` Balbir Singh [this message]
2016-04-09 6:13 ` [PATCH V2 42/68] powerpc/mm/radix: Isolate hash table function from pseries guest code Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 43/68] powerpc/mm/radix: Add checks in slice code to catch radix usage Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 44/68] powerpc/mm/radix: Limit paca allocation in radix Aneesh Kumar K.V
2016-04-22 8:07 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 45/68] powerpc/mm/radix: Pick the address layout for radix config Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 46/68] powerpc/mm/radix: Update secondary PTCR Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 47/68] powerpc/mm: Make a copy of pgalloc.h for 32 and 64 book3s Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 48/68] powerpc/mm: Copy pgalloc (part 2) Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 49/68] powerpc/mm: Revert changes made to nohash pgalloc-64.h Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 50/68] powerpc/mm: Simplify the code dropping 4 level table #ifdef Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 51/68] powerpc/mm: Rename function to indicate we are allocating fragments Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 52/68] powerpc/mm: make 4k and 64k use pte_t for pgtable_t Aneesh Kumar K.V
2016-04-26 2:58 ` Balbir Singh
2016-04-28 6:03 ` Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 53/68] powerpc/mm: Add radix pgalloc details Aneesh Kumar K.V
2016-04-26 3:05 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 54/68] powerpc/mm: Update pte filter for radix Aneesh Kumar K.V
2016-04-26 3:06 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 55/68] powerpc/mm: VMALLOC abstraction Aneesh Kumar K.V
2016-04-22 6:52 ` Michael Neuling
2016-04-23 3:29 ` Aneesh Kumar K.V
2016-04-26 6:20 ` Balbir Singh
2016-04-26 4:47 ` Balbir Singh
2016-04-28 6:09 ` Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 56/68] powerpc/radix: update mmu cache Aneesh Kumar K.V
2016-04-26 6:23 ` Balbir Singh
2016-04-09 6:13 ` [PATCH V2 57/68] powerpc/mm: pte_frag abstraction Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 58/68] powerpc/mm: Fix vma_mmu_pagesize for radix Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 59/68] powerpc/mm: Add radix support for hugetlb Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 60/68] powerpc/mm/radix: Make sure swapper pgdir is properly aligned Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 61/68] powerpc/mm/radix: Add hugetlb support 4K page size Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 62/68] powerpc/mm: Drop PTE_ATOMIC_UPDATES from pmd_hugepage_update Aneesh Kumar K.V
2016-04-09 6:13 ` [PATCH V2 63/68] powerpc/mm: THP is only available on hash64 as of now Aneesh Kumar K.V
2016-04-09 6:14 ` [PATCH V2 64/68] powerpc/mm/thp: Abstraction for THP functions Aneesh Kumar K.V
2016-04-09 6:14 ` [PATCH V2 65/68] powerpc/mm/radix: Add radix THP callbacks Aneesh Kumar K.V
2016-04-09 6:14 ` [PATCH V2 66/68] powerpc/mm/radix: Add THP support for 4k linux page size Aneesh Kumar K.V
2016-04-28 4:56 ` [V2, " Michael Ellerman
2016-04-28 6:28 ` Aneesh Kumar K.V
2016-04-09 6:14 ` [PATCH V2 67/68] powerpc/mm/radix: Cputable update for radix Aneesh Kumar K.V
2016-04-28 14:10 ` [V2,67/68] " Michael Ellerman
2016-04-09 6:14 ` [PATCH V2 68/68] powerpc/mm/radix: Use firmware feature to disable radix Aneesh Kumar K.V
2016-04-20 2:59 ` [V2, " Michael Ellerman
2016-04-20 8:21 ` Aneesh Kumar K.V
2016-04-20 11:25 ` Michael Neuling
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5719D3A1.8070008@gmail.com \
--to=bsingharora@gmail.com \
--cc=aneesh.kumar@linux.vnet.ibm.com \
--cc=benh@kernel.crashing.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.au \
--cc=paulus@samba.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.