diff for duplicates of <5720002.roQESv2v7G@wasted.cogentembedded.com> diff --git a/a/1.txt b/N1/1.txt index bcc1183..7428140 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -23,12 +23,12 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + }; /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { + mstp1_clks: mstp1_clks at e6150134 { @@ -533,6 +540,15 @@ >; clock-output-names = "sys-dmac1", "sys-dmac0"; }; -+ mstp3_clks: mstp3_clks@e615013c { ++ mstp3_clks: mstp3_clks at e615013c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; @@ -37,6 +37,6 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + renesas,clock-indices = <R8A7792_CLK_SDHI0>; + clock-output-names = "sdhi0"; + }; - mstp4_clks: mstp4_clks@e6150140 { + mstp4_clks: mstp4_clks at e6150140 { compatible = "renesas,r8a7792-mstp-clocks", "renesas,cpg-mstp-clocks"; diff --git a/a/content_digest b/N1/content_digest index 38cd0fb..fee0497 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,15 +1,8 @@ "ref\02441635.ESeLhIjWEX@wasted.cogentembedded.com\0" - "From\0Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\0" + "From\0sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)\0" "Subject\0[PATCH 1/2] ARM: dts: r8a7792: add SD clocks\0" "Date\0Wed, 13 Jul 2016 00:10:18 +0300\0" - "To\0horms@verge.net.au" - linux-renesas-soc@vger.kernel.org - robh+dt@kernel.org - mark.rutland@arm.com - " devicetree@vger.kernel.org\0" - "Cc\0magnus.damm@gmail.com" - linux@arm.linux.org.uk - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Describe the SDHI0 clock and its parent, SD clock in the R8A7792 device tree.\n" @@ -37,12 +30,12 @@ "+\t\t};\n" " \n" " \t\t/* Gate clocks */\n" - " \t\tmstp1_clks: mstp1_clks@e6150134 {\n" + " \t\tmstp1_clks: mstp1_clks at e6150134 {\n" "@@ -533,6 +540,15 @@\n" " \t\t\t>;\n" " \t\t\tclock-output-names = \"sys-dmac1\", \"sys-dmac0\";\n" " \t\t};\n" - "+\t\tmstp3_clks: mstp3_clks@e615013c {\n" + "+\t\tmstp3_clks: mstp3_clks at e615013c {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;\n" @@ -51,8 +44,8 @@ "+\t\t\trenesas,clock-indices = <R8A7792_CLK_SDHI0>;\n" "+\t\t\tclock-output-names = \"sdhi0\";\n" "+\t\t};\n" - " \t\tmstp4_clks: mstp4_clks@e6150140 {\n" + " \t\tmstp4_clks: mstp4_clks at e6150140 {\n" " \t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" " \t\t\t\t \"renesas,cpg-mstp-clocks\";" -5eb31da99057fbad7cd050288aa2afdfb139f3f5b0f5578166a1ad2ad48a6c38 +7e42a8ffe2c34b614a316c3b0f68fa66f36d439edf8cc2d4c9c71dfa142ac26e
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