From: Julien Grall <julien.grall@arm.com>
To: Wei Chen <wei.chen@linaro.org>
Cc: Stefano Stabellini <sstabellini@kernel.org>,
steve.capper@arm.com, suravee.suthikulpanit@amd.com,
xen-devel@lists.xen.org
Subject: Re: [PATCH v2] xen/arm: gicv2: Export GICv2m register frames to domain0 by device tree
Date: Wed, 27 Apr 2016 10:40:29 +0100 [thread overview]
Message-ID: <5720890D.80806@arm.com> (raw)
In-Reply-To: <CANta1d8sEcnyKp+yQn3R_-VBb2jBHYKOni-Vt-L9n_pwjHSMHw@mail.gmail.com>
On 27/04/2016 07:05, Wei Chen wrote:
> Hi Julien,
Hi Wei,
> On 26 April 2016 at 18:49, Julien Grall <julien.grall@arm.com> wrote:
>> On 25/04/2016 10:39, Wei Chen wrote:
>>> + d->domain_id);
>>> + return ret;
>>> + }
>>> +
>>> + /*
>>> + * Map all SPIs that are allocated to MSIs for the frame to the
>>> + * domain.
>>> + */
>>> + for ( spi = v2m_data->spi_start;
>>> + spi < (v2m_data->spi_start + v2m_data->nr_spis); spi++ )
>>> + {
>>> + /*
>>> + * MSIs are always edge-triggered. Configure the associated
>>> SPIs
>>> + * to be edge-rising.
>>
>>
>> How did you find that SPIs should be configured edge-rising?
> Before route_irq_to_guest, the SPI must be configured. I found Linux
> v2m driver set
> the SPI type to edge-rising, so I set edge-rising as v2m SPI default
> type here too.
Well, Linux did it for a good reason (i.e based on a spec). We are
trying in Xen to document piece of code which may not be
straight-forward to deduce.
In this case, the IRQ is configured edge-rising because this is the only
edge type supported by SPIs. I would expand the second sentence of the
comment to explain that.
Regards,
--
Julien Grall
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next prev parent reply other threads:[~2016-04-27 9:40 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-25 9:39 [PATCH v2] xen/arm: gicv2: Export GICv2m register frames to domain0 by device tree Wei Chen
2016-04-26 10:49 ` Julien Grall
2016-04-27 6:05 ` Wei Chen
2016-04-27 9:40 ` Julien Grall [this message]
2016-04-28 2:08 ` Wei Chen
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