From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47190) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avgR3-0004Nn-1A for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:32:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1avgQz-0005Zw-OB for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:32:28 -0400 Received: from mout.web.de ([212.227.17.11]:53037) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avgQz-0005Zr-EO for qemu-devel@nongnu.org; Thu, 28 Apr 2016 03:32:25 -0400 References: <1461827144-6937-1-git-send-email-peterx@redhat.com> <1461827144-6937-11-git-send-email-peterx@redhat.com> From: Jan Kiszka Message-ID: <5721BC81.9070708@web.de> Date: Thu, 28 Apr 2016 09:32:17 +0200 MIME-Version: 1.0 In-Reply-To: <1461827144-6937-11-git-send-email-peterx@redhat.com> Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 10/18] intel_iommu: Add support for PCI MSI remap List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu , qemu-devel@nongnu.org Cc: imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On 2016-04-28 09:05, Peter Xu wrote: > This patch enables interrupt remapping for PCI devices. > > To play the trick, one memory region "iommu_ir" is added as child region > of the original iommu memory region, covering range 0xfeeXXXXX (which is > the address range for APIC). All the writes to this range will be taken > as MSI, and translation is carried out only when IR is enabled. > > Idea suggested by Paolo Bonzini. This still lacks source (device ID) identification, right? Were did the memory write attribute thing go? Given that you actually introduce a separate MSI target address space for the IOAPIC (btw, once there will be more than one instance, like on real hw today) and that you will need yet another one for each HPET, why not address this with a common scheme now, ie. by transmitting the source ID along the write via that attribute? Jan