From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49656) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aviJN-0007oi-Tm for qemu-devel@nongnu.org; Thu, 28 Apr 2016 05:32:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aviJI-0001Nh-U5 for qemu-devel@nongnu.org; Thu, 28 Apr 2016 05:32:41 -0400 Received: from mout.web.de ([212.227.17.11]:52450) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aviJI-0001NY-LB for qemu-devel@nongnu.org; Thu, 28 Apr 2016 05:32:36 -0400 References: <1461827144-6937-1-git-send-email-peterx@redhat.com> <5721B980.4050903@web.de> <20160428091802.GH20143@pxdev.xzpeter.org> From: Jan Kiszka Message-ID: <5721D8A3.6010302@web.de> Date: Thu, 28 Apr 2016 11:32:19 +0200 MIME-Version: 1.0 In-Reply-To: <20160428091802.GH20143@pxdev.xzpeter.org> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 00/18] IOMMU: Enable interrupt remapping for Intel IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu Cc: qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On 2016-04-28 11:18, Peter Xu wrote: > On Thu, Apr 28, 2016 at 09:19:28AM +0200, Jan Kiszka wrote: >> On 2016-04-28 09:05, Peter Xu wrote: >>> v5 changes: >>> - patch 10: add vector checking for IOAPIC interrupts (this may help >>> debug in the future, will only generate warning if specify >>> IOMMU_DEBUG) >>> - patch 13: replace error_report() with a trace. [Jan] >>> - patch 14: rename parameter "intr" to "intremap", to be aligned >>> with kernel parameter [Jan] >>> - patch 15: fix comments for vtd_iec_notify_fn >>> - patch 17 & 18 (added): fix issue when IR enabled with devices >>> using level-triggered interrupts, like e1000. Adding it to the end >>> of series, since this issue never happen without IR. >>> >>> Patch 17 adds read-only check for IOAPIC entries. >>> Patch 18 clears remote IRR bit when entry configured as >>> edge-triggered. >> >> IIUC, your series does not address irqfd yet, only by chance if the >> target is an IOAPIC pin for which you set up routes now. Correct? > > Ah, yes, vhost and vfio should be in the notifier list as well. I > just missed that. :( > > If not consider the IEC invalidation, the series should work for > irqfd, right? Hmm, yeah - you are hooking to the route update path and translate what the kernel will get. > >> >> Instead of fiddling with irq routes for the IOAPIC - where we don't need >> it -, I would suggest to do the following: Send IOAPIC events via >> kvm_irqchip_send_msi to the kernel. Only irqfd users (vhost, vfio) >> should use the pattern you are now applying to the IOAPIC: establish >> static routes as an irqfd is set up, and that route should be translated >> by the iommu first, register an IEC notifier to update any affected >> route when the iommu translation changes. > > Yes, maybe that's the right thing to do. Or say, when split irqchip, > IOAPIC can avoid using GSI routes any more. If with that, I should > also remove lots of things, like: IEC notifiers for IOAPIC, and all > things related to msi route sync-up in IOAPIC codes with KVM (so I > suppose we will save 24 gsi route entries for KVM, which sounds > good). Right. > > (Ah... I think the series is keep growing...) (Looks like I'm contributing to it, sorry ;) ) Jan