From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51999) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1awnTa-0006u2-LU for qemu-devel@nongnu.org; Sun, 01 May 2016 05:15:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1awnTO-0007UC-Pf for qemu-devel@nongnu.org; Sun, 01 May 2016 05:15:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:49116) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1awnTO-0007SD-I0 for qemu-devel@nongnu.org; Sun, 01 May 2016 05:15:30 -0400 References: <1461969763-5193-1-git-send-email-davidkiarie4@gmail.com> <1461969763-5193-5-git-send-email-davidkiarie4@gmail.com> From: Marcel Apfelbaum Message-ID: <5725C921.7060108@redhat.com> Date: Sun, 1 May 2016 12:15:13 +0300 MIME-Version: 1.0 In-Reply-To: <1461969763-5193-5-git-send-email-davidkiarie4@gmail.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [V9 4/4] hw/pci-host: Emulate AMD IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Kiarie , qemu-devel@nongnu.org Cc: jan.kiszka@web.de, valentine.sinitsyn@gmail.com, imammedo@redhat.com, mst@redhat.com, peterx@redhat.com On 04/30/2016 01:42 AM, David Kiarie wrote: > Add AMD IOMMU emulation support to q35 chipset > > Signed-off-by: David Kiarie > --- > hw/pci-host/q35.c | 25 ++++++++++++++++++++++--- > include/hw/i386/intel_iommu.h | 2 +- > 2 files changed, 23 insertions(+), 4 deletions(-) > > diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c > index 70f897e..b4e1bfe 100644 > --- a/hw/pci-host/q35.c > +++ b/hw/pci-host/q35.c > @@ -32,6 +32,7 @@ > #include "hw/pci-host/q35.h" > #include "qapi/error.h" > #include "qapi/visitor.h" > +#include "hw/i386/amd_iommu.h" > > /**************************************************************************** > * Q35 host > @@ -448,6 +449,19 @@ static void mch_init_dmar(MCHPCIState *mch) > pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); > } > > +static void mch_init_amdvi(MCHPCIState *mch) > +{ > + AMDIOMMUState *iommu_state; > + PCIBus *bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); > + PCIDevice *iommu; > + > + iommu = pci_create_simple(bus, 0x20, TYPE_AMD_IOMMU_DEVICE); > + > + iommu_state = AMD_IOMMU_DEVICE(iommu); > + > + pci_setup_iommu(bus, bridge_host_amd_iommu, iommu_state); > +} > + > static void mch_realize(PCIDevice *d, Error **errp) > { > int i; > @@ -506,9 +520,14 @@ static void mch_realize(PCIDevice *d, Error **errp) > mch->pci_address_space, &mch->pam_regions[i+1], > PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); > } > - /* Intel IOMMU (VT-d) */ > - if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { > - mch_init_dmar(mch); > + > + MachineState *machine = MACHINE(qdev_get_machine()); > + if (machine->iommu) { > + if (machine->iommu_type == TYPE_AMD) { > + mch_init_amdvi(mch); > + } else { > + mch_init_dmar(mch); > + } > } > } > > diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h > index 7e511e1..539530c 100644 > --- a/include/hw/i386/intel_iommu.h > +++ b/include/hw/i386/intel_iommu.h > @@ -24,10 +24,10 @@ > #include "hw/qdev.h" > #include "sysemu/dma.h" > > -#define INTEL_IOMMU_STR "intel" > #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" > #define INTEL_IOMMU_DEVICE(obj) \ > OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) > +#define INTEL_IOMMU_STR "intel" I am not sure why you needed this chunck and if Michael will accept the hard-coded 0x20 address for the AMD IOMMU, but the realization code looks good to me. Reviewed-by: Marcel Apfelbaum Thanks, Marcel > > /* DMAR Hardware Unit Definition address (IOMMU unit) */ > #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL >