From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH 0/6] soc/tegra: Add support for IO pads control via pinctrl interface Date: Tue, 3 May 2016 12:38:41 +0100 Message-ID: <57288DC1.20405@nvidia.com> References: <1462191434-28933-1-git-send-email-ldewangan@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1462191434-28933-1-git-send-email-ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Laxman Dewangan , swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org, linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Cc: linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-gpio@vger.kernel.org On 02/05/16 13:17, Laxman Dewangan wrote: > The IO pins of Tegra SoCs are grouped for common control of IO > interface like setting voltage signal levels and power state of > the interface. The group is generally referred as IO pads. The > power state and voltage control of IO pins can be done at IO pads > level. > > Before Tegra210, the voltage level of IO rails are auto detected and > configure IO pads accordingly but on T210, it is require to set > explicitly by SW. > > This series: > - add public APIs from Tegra PMC interface for io pads control > for power state and voltage levels. > - Add pincontrol driver to use these APIs to configure the IO > pads voltage and power state. > > --- > Changes from V1: > - Use pinconfig generic property for power enable/disable. > - Rename power-source-voltage properties. > - Make all register read/write value to u32. > - Add IO pads macros and APIs which is nearest definiton of HW blocks. Nit ... if this is a V2 it should be stated in the subject. Jon From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756005AbcECLiu (ORCPT ); Tue, 3 May 2016 07:38:50 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14761 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755791AbcECLis (ORCPT ); Tue, 3 May 2016 07:38:48 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 03 May 2016 04:38:11 -0700 Subject: Re: [PATCH 0/6] soc/tegra: Add support for IO pads control via pinctrl interface To: Laxman Dewangan , , , , , , References: <1462191434-28933-1-git-send-email-ldewangan@nvidia.com> CC: , , , From: Jon Hunter Message-ID: <57288DC1.20405@nvidia.com> Date: Tue, 3 May 2016 12:38:41 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1462191434-28933-1-git-send-email-ldewangan@nvidia.com> X-Originating-IP: [10.21.132.133] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/05/16 13:17, Laxman Dewangan wrote: > The IO pins of Tegra SoCs are grouped for common control of IO > interface like setting voltage signal levels and power state of > the interface. The group is generally referred as IO pads. The > power state and voltage control of IO pins can be done at IO pads > level. > > Before Tegra210, the voltage level of IO rails are auto detected and > configure IO pads accordingly but on T210, it is require to set > explicitly by SW. > > This series: > - add public APIs from Tegra PMC interface for io pads control > for power state and voltage levels. > - Add pincontrol driver to use these APIs to configure the IO > pads voltage and power state. > > --- > Changes from V1: > - Use pinconfig generic property for power enable/disable. > - Rename power-source-voltage properties. > - Make all register read/write value to u32. > - Add IO pads macros and APIs which is nearest definiton of HW blocks. Nit ... if this is a V2 it should be stated in the subject. Jon