From mboxrd@z Thu Jan 1 00:00:00 1970 From: "J.D. Schroeder" Subject: Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency Date: Tue, 3 May 2016 08:31:11 -0500 Message-ID: <5728A81F.4050906@garmin.com> References: <20160427171658.GA5995@atomide.com> <1462209123-7332-1-git-send-email-Linux.HWI@garmin.com> <1462209123-7332-3-git-send-email-Linux.HWI@garmin.com> <57285E66.2000708@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <57285E66.2000708@ti.com> Sender: linux-kernel-owner@vger.kernel.org To: Tero Kristo , linux-kernel@vger.kernel.org, bcousson@baylibre.com, tony@atomide.com, robh+dt@kernel.org, pawel.moll@arm.com, mark.rutland@arm.com, ijc+devicetree@hellion.org.uk, galak@codeaurora.org, linux@arm.linux.org.uk, linux-omap@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: jay.schroeder@garmin.com List-Id: linux-omap@vger.kernel.org On 05/03/2016 03:16 AM, Tero Kristo wrote: > On 02/05/16 20:12, J.D. Schroeder wrote: >> From: "J.D. Schroeder" >> >> This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency >> from the precise 32kHz frequency (i.e., 32.768 kHz) to a more >> accurate frequency of ~34.6 kHz. Actual measured frequencies of the >> clock vary from processor to processor anywhere from 34.4 kHz up to >> 34.8 kHz. Note that the ~34 kHz frequency clock is generated >> internally by the processor, not an input to the processor. This >> change makes it more clear that the consumer of the >> secure_32k_clk_src_ck will not get a precise 32.768 kHz frequency >> output. >> >> Signed-off-by: J.D. Schroeder >> Reviewed-by: Trenton Andres >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 3f0c61d..f7ec976 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -95,7 +95,7 @@ >> secure_32k_clk_src_ck: secure_32k_clk_src_ck { >> #clock-cells = <0>; >> compatible = "fixed-clock"; >> - clock-frequency = <32768>; >> + clock-frequency = <34600>; /* approximate frequency */ >> }; >> >> sys_clk32_crystal_ck: sys_clk32_crystal_ck { >> > > I still don't agree with this patch. The actual frequency can drift much more, > you are just seeing this number at your setup. Yes, it can drift significantly from processor to processor. Do you agree that this frequency is closer to what can be expected than 32768 Hz? Like I said, I would have renamed the clock also but I opted to go the less obtrusive route while still helping others that might think they can reasonably use this clock in their design as a 32768 Hz clock source. Perhaps my comment and selection of the approximate frequency is not the best (I'm open for suggestions). However, I do think this change is an improvement and clarifying change to what is currently present in the clock description. -JD From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linux.HWI@garmin.com (J.D. Schroeder) Date: Tue, 3 May 2016 08:31:11 -0500 Subject: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency In-Reply-To: <57285E66.2000708@ti.com> References: <20160427171658.GA5995@atomide.com> <1462209123-7332-1-git-send-email-Linux.HWI@garmin.com> <1462209123-7332-3-git-send-email-Linux.HWI@garmin.com> <57285E66.2000708@ti.com> Message-ID: <5728A81F.4050906@garmin.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 05/03/2016 03:16 AM, Tero Kristo wrote: > On 02/05/16 20:12, J.D. Schroeder wrote: >> From: "J.D. Schroeder" >> >> This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency >> from the precise 32kHz frequency (i.e., 32.768 kHz) to a more >> accurate frequency of ~34.6 kHz. Actual measured frequencies of the >> clock vary from processor to processor anywhere from 34.4 kHz up to >> 34.8 kHz. Note that the ~34 kHz frequency clock is generated >> internally by the processor, not an input to the processor. This >> change makes it more clear that the consumer of the >> secure_32k_clk_src_ck will not get a precise 32.768 kHz frequency >> output. >> >> Signed-off-by: J.D. Schroeder >> Reviewed-by: Trenton Andres >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 3f0c61d..f7ec976 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -95,7 +95,7 @@ >> secure_32k_clk_src_ck: secure_32k_clk_src_ck { >> #clock-cells = <0>; >> compatible = "fixed-clock"; >> - clock-frequency = <32768>; >> + clock-frequency = <34600>; /* approximate frequency */ >> }; >> >> sys_clk32_crystal_ck: sys_clk32_crystal_ck { >> > > I still don't agree with this patch. The actual frequency can drift much more, > you are just seeing this number at your setup. Yes, it can drift significantly from processor to processor. Do you agree that this frequency is closer to what can be expected than 32768 Hz? Like I said, I would have renamed the clock also but I opted to go the less obtrusive route while still helping others that might think they can reasonably use this clock in their design as a 32768 Hz clock source. Perhaps my comment and selection of the approximate frequency is not the best (I'm open for suggestions). However, I do think this change is an improvement and clarifying change to what is currently present in the clock description. -JD From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756011AbcECNbW (ORCPT ); Tue, 3 May 2016 09:31:22 -0400 Received: from mail-by2on0145.outbound.protection.outlook.com ([207.46.100.145]:20480 "EHLO na01-by2-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1755569AbcECNbT (ORCPT ); Tue, 3 May 2016 09:31:19 -0400 Authentication-Results: spf=pass (sender IP is 204.77.163.247) smtp.mailfrom=garmin.com; hellion.org.uk; dkim=none (message not signed) header.d=none;hellion.org.uk; dmarc=bestguesspass action=none header.from=garmin.com; Subject: Re: [PATCH v2 2/3] ARM: DRA7x: dts: Update the OSC_32K_CLK frequency To: Tero Kristo , , , , , , , , , , , , References: <20160427171658.GA5995@atomide.com> <1462209123-7332-1-git-send-email-Linux.HWI@garmin.com> <1462209123-7332-3-git-send-email-Linux.HWI@garmin.com> <57285E66.2000708@ti.com> CC: From: "J.D. Schroeder" Message-ID: <5728A81F.4050906@garmin.com> Date: Tue, 3 May 2016 08:31:11 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <57285E66.2000708@ti.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-TM-AS-Product-Ver: SMEX-11.0.0.4179-8.000.1202-22298.007 X-TM-AS-Result: No--7.536400-0.000000-31 X-TM-AS-User-Approved-Sender: Yes X-TM-AS-User-Blocked-Sender: No X-EOPAttributedMessage: 0 X-Forefront-Antispam-Report: CIP:204.77.163.247;IPV:NLI;CTRY:US;EFV:NLI;SFV:NSPM;SFS:(10019020)(6009001)(2980300002)(438002)(189002)(24454002)(199003)(377454003)(64126003)(33656002)(93886004)(106466001)(92566002)(36756003)(107886002)(1220700001)(40036005)(47776003)(189998001)(86362001)(575784001)(230700001)(80316001)(65816999)(6806005)(76176999)(50986999)(54356999)(19580405001)(5008740100001)(16796002)(19580395003)(65956001)(65806001)(15650500001)(8936002)(50466002)(11100500001)(83506001)(4326007)(87936001)(59896002)(4001430100002)(2201001)(23746002)(81166005)(4001350100001)(77096005)(5001770100001)(586003)(2950100001)(921003)(83996005)(2101003)(1121003);DIR:OUT;SFP:1102;SCL:1;SRVR:BN3PR0401MB1332;H:garmin.com;FPR:;SPF:Pass;MLV:sfv;MX:1;A:1;LANG:en; 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Schroeder wrote: >> From: "J.D. Schroeder" >> >> This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency >> from the precise 32kHz frequency (i.e., 32.768 kHz) to a more >> accurate frequency of ~34.6 kHz. Actual measured frequencies of the >> clock vary from processor to processor anywhere from 34.4 kHz up to >> 34.8 kHz. Note that the ~34 kHz frequency clock is generated >> internally by the processor, not an input to the processor. This >> change makes it more clear that the consumer of the >> secure_32k_clk_src_ck will not get a precise 32.768 kHz frequency >> output. >> >> Signed-off-by: J.D. Schroeder >> Reviewed-by: Trenton Andres >> --- >> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> index 3f0c61d..f7ec976 100644 >> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi >> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi >> @@ -95,7 +95,7 @@ >> secure_32k_clk_src_ck: secure_32k_clk_src_ck { >> #clock-cells = <0>; >> compatible = "fixed-clock"; >> - clock-frequency = <32768>; >> + clock-frequency = <34600>; /* approximate frequency */ >> }; >> >> sys_clk32_crystal_ck: sys_clk32_crystal_ck { >> > > I still don't agree with this patch. The actual frequency can drift much more, > you are just seeing this number at your setup. Yes, it can drift significantly from processor to processor. Do you agree that this frequency is closer to what can be expected than 32768 Hz? Like I said, I would have renamed the clock also but I opted to go the less obtrusive route while still helping others that might think they can reasonably use this clock in their design as a 32768 Hz clock source. Perhaps my comment and selection of the approximate frequency is not the best (I'm open for suggestions). However, I do think this change is an improvement and clarifying change to what is currently present in the clock description. -JD