From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field definition Date: Fri, 6 May 2016 15:12:25 +0100 Message-ID: <572CA649.70401@nvidia.com> References: <1462531548-12914-1-git-send-email-ldewangan@nvidia.com> <1462531548-12914-2-git-send-email-ldewangan@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1462531548-12914-2-git-send-email-ldewangan@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laxman Dewangan , thierry.reding@gmail.com, airlied@linux.ie, swarren@wwwdotorg.org, gnurou@gmail.com Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: linux-tegra@vger.kernel.org Ck9uIDA2LzA1LzE2IDExOjQ1LCBMYXhtYW4gRGV3YW5nYW4gd3JvdGU6Cj4gVXNlIEJJVCBtYWNy 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dHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4v bGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758266AbcEFOMe (ORCPT ); Fri, 6 May 2016 10:12:34 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:8068 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757430AbcEFOMc (ORCPT ); Fri, 6 May 2016 10:12:32 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Fri, 06 May 2016 07:11:16 -0700 Subject: Re: [PATCH V4 1/3] soc/tegra: pmc: Use BIT macro for register field definition To: Laxman Dewangan , , , , References: <1462531548-12914-1-git-send-email-ldewangan@nvidia.com> <1462531548-12914-2-git-send-email-ldewangan@nvidia.com> CC: , , X-Nvconfidentiality: public From: Jon Hunter Message-ID: <572CA649.70401@nvidia.com> Date: Fri, 6 May 2016 15:12:25 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1462531548-12914-2-git-send-email-ldewangan@nvidia.com> X-Originating-IP: [10.21.132.133] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/05/16 11:45, Laxman Dewangan wrote: > Use BIT macro for register field definition and make constant as U > when using in shift operator like (3 << 30) to (3U << 30) > > Signed-off-by: Laxman Dewangan > > --- > Changes from V1: > - Remove the indenting of line which is not for BIT macro usage. > Changes from V2: > - None > --- > drivers/soc/tegra/pmc.c | 40 ++++++++++++++++++++-------------------- > 1 file changed, 20 insertions(+), 20 deletions(-) > > diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c > index bb17345..2c3f1f9 100644 > --- a/drivers/soc/tegra/pmc.c > +++ b/drivers/soc/tegra/pmc.c > @@ -45,28 +45,28 @@ > #include > > #define PMC_CNTRL 0x0 > -#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ > -#define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */ > -#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ > -#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ > -#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ > -#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */ > +#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */ > +#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */ > +#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */ > +#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */ > +#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */ > +#define PMC_CNTRL_INTR_POLARITY BIT(17)/* inverts INTR polarity */ > > #define DPD_SAMPLE 0x020 > -#define DPD_SAMPLE_ENABLE (1 << 0) > -#define DPD_SAMPLE_DISABLE (0 << 0) > +#define DPD_SAMPLE_ENABLE BIT(0) > +#define DPD_SAMPLE_DISABLE (0 << 0) > > #define PWRGATE_TOGGLE 0x30 > -#define PWRGATE_TOGGLE_START (1 << 8) > +#define PWRGATE_TOGGLE_START BIT(8) > > #define REMOVE_CLAMPING 0x34 > > #define PWRGATE_STATUS 0x38 > > #define PMC_SCRATCH0 0x50 > -#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) > -#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) > -#define PMC_SCRATCH0_MODE_RCM (1 << 1) > +#define PMC_SCRATCH0_MODE_RECOVERY BIT(31) > +#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) > +#define PMC_SCRATCH0_MODE_RCM BIT(1) > #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ > PMC_SCRATCH0_MODE_BOOTLOADER | \ > PMC_SCRATCH0_MODE_RCM) > @@ -77,14 +77,14 @@ > #define PMC_SCRATCH41 0x140 > > #define PMC_SENSOR_CTRL 0x1b0 > -#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2) > -#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1) > +#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2) > +#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1) > > #define IO_DPD_REQ 0x1b8 > -#define IO_DPD_REQ_CODE_IDLE (0 << 30) > -#define IO_DPD_REQ_CODE_OFF (1 << 30) > -#define IO_DPD_REQ_CODE_ON (2 << 30) > -#define IO_DPD_REQ_CODE_MASK (3 << 30) > +#define IO_DPD_REQ_CODE_IDLE (0 << 30) > +#define IO_DPD_REQ_CODE_OFF (1U << 30) > +#define IO_DPD_REQ_CODE_ON (2U << 30) > +#define IO_DPD_REQ_CODE_MASK (3U << 30) > > #define IO_DPD_STATUS 0x1bc > #define IO_DPD2_REQ 0x1c0 > @@ -96,10 +96,10 @@ > #define PMC_SCRATCH54_ADDR_SHIFT 0 > > #define PMC_SCRATCH55 0x25c > -#define PMC_SCRATCH55_RESET_TEGRA (1 << 31) > +#define PMC_SCRATCH55_RESET_TEGRA BIT(31) > #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27 > #define PMC_SCRATCH55_PINMUX_SHIFT 24 > -#define PMC_SCRATCH55_16BITOP (1 << 15) > +#define PMC_SCRATCH55_16BITOP BIT(15) > #define PMC_SCRATCH55_CHECKSUM_SHIFT 16 > #define PMC_SCRATCH55_I2CSLV1_SHIFT 0 Acked-by: Jon Hunter Cheers Jon