From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:55444)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <jan.kiszka@web.de>) id 1az2q3-0004ve-IR
	for qemu-devel@nongnu.org; Sat, 07 May 2016 10:04:12 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <jan.kiszka@web.de>) id 1az2py-0007cA-4Y
	for qemu-devel@nongnu.org; Sat, 07 May 2016 10:04:11 -0400
Received: from mout.web.de ([212.227.15.14]:62592)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <jan.kiszka@web.de>) id 1az2px-0007c4-Ot
	for qemu-devel@nongnu.org; Sat, 07 May 2016 10:04:06 -0400
References: <1462568028-31037-1-git-send-email-rkrcmar@redhat.com>
	<1462568028-31037-5-git-send-email-rkrcmar@redhat.com>
From: Jan Kiszka <jan.kiszka@web.de>
Message-ID: <572DF5C8.7070105@web.de>
Date: Sat, 7 May 2016 16:03:52 +0200
MIME-Version: 1.0
In-Reply-To: <1462568028-31037-5-git-send-email-rkrcmar@redhat.com>
Content-Type: text/plain; charset=utf-8
Content-Transfer-Encoding: 8bit
Subject: Re: [Qemu-devel] [PATCH 4/4] kvm: support MSI_X2APIC capability
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= <rkrcmar@redhat.com>, qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>, "Lan, Tianyu" <tianyu.lan@intel.com>, Igor Mammedov <imammedo@redhat.com>, Peter Xu <peterx@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Richard Henderson <rth@twiddle.net>

On 2016-05-06 22:53, Radim Krčmář wrote:
> The capability alows us to express x2APIC destinations.

"allows"

Will the possibility to create >254 CPUs be indirectly coupled to this
capability, or should userland check for it explicitly then?

Will the kernel handle the case gracefully that AMD CPUs will report the
capability as well, although there is no x2APIC (at least so far) with
those CPU types, and we still inject MSI messages with that flag set
(just to double-check if the case was thought through)?

Jan