diff for duplicates of <5730BF59.4070905@opensource.altera.com> diff --git a/a/1.txt b/N1/1.txt index 1988f7c..78ccf75 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,354 +1,381 @@ + On 05/09/2016 11:02 AM, Lee Jones wrote: -> On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote: -> ->> From: Thor Thayer <tthayer@opensource.altera.com> ->> ->> Add support for the Altera Arria10 Development Kit System Resource ->> chip which is implemented using a MAX5 as a external gpio extender, ->> and power supply alarm (hwmon) with the regmap framework over a SPI bus. ->> ->> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com> ->> --- ->> drivers/mfd/Kconfig | 11 +++ ->> drivers/mfd/Makefile | 2 + ->> drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++ ->> include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++ ->> 4 files changed, 279 insertions(+) ->> create mode 100644 drivers/mfd/altera-a10sr.c ->> create mode 100644 include/linux/mfd/altera-a10sr.h ->> ->> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig ->> index eea61e3..4fc27c6 100644 ->> --- a/drivers/mfd/Kconfig ->> +++ b/drivers/mfd/Kconfig ->> @@ -18,6 +18,17 @@ config MFD_CS5535 ->> This is the core driver for CS5535/CS5536 MFD functions. This is ->> necessary for using the board's GPIO and MFGPT functionality. ->> ->> +config MFD_ALTERA_A10SR ->> + bool "Altera Arria10 DevKit System Resource chip" ->> + depends on ARCH_SOCFPGA && SPI_MASTER=y && OF ->> + select REGMAP_SPI ->> + select MFD_CORE ->> + help ->> + Support for the Altera Arria10 DevKit MAX5 System Resource chip ->> + using the SPI interface. This driver provides common support for ->> + accessing the external gpio extender (LEDs & buttons) and ->> + power supply alarms (hwmon). ->> + ->> config MFD_ACT8945A ->> tristate "Active-semi ACT8945A" ->> select MFD_CORE ->> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile ->> index 5eaa6465d..4f1ff91 100644 ->> --- a/drivers/mfd/Makefile ->> +++ b/drivers/mfd/Makefile ->> @@ -203,3 +203,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o intel_soc_pmic_crc.o ->> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o ->> obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o ->> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o ->> + ->> +obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o ->> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c ->> new file mode 100644 ->> index 0000000..2ff08e3 ->> --- /dev/null ->> +++ b/drivers/mfd/altera-a10sr.c ->> @@ -0,0 +1,179 @@ ->> +/* ->> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved ->> + * ->> + * This program is free software; you can redistribute it and/or modify it ->> + * under the terms and conditions of the GNU General Public License, ->> + * version 2, as published by the Free Software Foundation. ->> + * ->> + * This program is distributed in the hope it will be useful, but WITHOUT ->> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ->> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ->> + * more details. ->> + * ->> + * You should have received a copy of the GNU General Public License along with ->> + * this program. If not, see <http://www.gnu.org/licenses/>. ->> + * ->> + * SPI access for Altera Arria10 MAX5 System Resource Chip ->> + * ->> + * Adapted from DA9052 ->> + * Copyright(c) 2011 Dialog Semiconductor Ltd. ->> + * Author: David Dajun Chen <dchen@diasemi.com> -> -> You don't need to carry the copyright or authorship tags over. -> + +On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote: + + +From: Thor Thayer <ttha...@opensource.altera.com> +To: linux-hwmon@vger.kernel.org + +Add support for the Altera Arria10 Development Kit System Resource +chip which is implemented using a MAX5 as a external gpio extender, +and power supply alarm (hwmon) with the regmap framework over a SPI bus. + +Signed-off-by: Thor Thayer <ttha...@opensource.altera.com> +--- + drivers/mfd/Kconfig | 11 +++ + drivers/mfd/Makefile | 2 + + drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++ + include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++ + 4 files changed, 279 insertions(+) + create mode 100644 drivers/mfd/altera-a10sr.c + create mode 100644 include/linux/mfd/altera-a10sr.h + +diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig +index eea61e3..4fc27c6 100644 +--- a/drivers/mfd/Kconfig ++++ b/drivers/mfd/Kconfig +@@ -18,6 +18,17 @@ config MFD_CS5535 + This is the core driver for CS5535/CS5536 MFD functions. This is + necessary for using the board's GPIO and MFGPT functionality. + ++config MFD_ALTERA_A10SR ++ bool "Altera Arria10 DevKit System Resource chip" ++ depends on ARCH_SOCFPGA && SPI_MASTER=y && OF ++ select REGMAP_SPI ++ select MFD_CORE ++ help ++ Support for the Altera Arria10 DevKit MAX5 System Resource chip ++ using the SPI interface. This driver provides common support for ++ accessing the external gpio extender (LEDs & buttons) and ++ power supply alarms (hwmon). ++ + config MFD_ACT8945A + tristate "Active-semi ACT8945A" + select MFD_CORE +diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile +index 5eaa6465d..4f1ff91 100644 +--- a/drivers/mfd/Makefile ++++ b/drivers/mfd/Makefile +@@ -203,3 +203,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o +intel_soc_pmic_crc.o + intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o + obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o + obj-$(CONFIG_MFD_MT6397) += mt6397-core.o ++ ++obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o +diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c +new file mode 100644 +index 0000000..2ff08e3 +--- /dev/null ++++ b/drivers/mfd/altera-a10sr.c +@@ -0,0 +1,179 @@ ++/* ++ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see <http://www.gnu.org/licenses/>. ++ * ++ * SPI access for Altera Arria10 MAX5 System Resource Chip ++ * ++ * Adapted from DA9052 ++ * Copyright(c) 2011 Dialog Semiconductor Ltd. ++ * Author: David Dajun Chen <dc...@diasemi.com> + + +You don't need to carry the copyright or authorship tags over. + + OK. Thanks, ->> + */ ->> + ->> +#include <linux/mfd/altera-a10sr.h> ->> +#include <linux/mfd/core.h> ->> +#include <linux/module.h> ->> +#include <linux/of.h> ->> +#include <linux/spi/spi.h> ->> + ->> +static const struct mfd_cell altr_a10sr_subdev_info[] = { ->> + { ->> + .name = "altr_a10sr_gpio", ->> + .of_compatible = "altr,a10sr-gpio", ->> + }, ->> +}; ->> + ->> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg) ->> +{ ->> + switch (reg) { ->> + case ALTR_A10SR_VERSION_READ: ->> + case ALTR_A10SR_LED_REG: ->> + case ALTR_A10SR_PBDSW_REG: ->> + case ALTR_A10SR_PBDSW_IRQ_REG: ->> + case ALTR_A10SR_PWR_GOOD1_REG: ->> + case ALTR_A10SR_PWR_GOOD2_REG: ->> + case ALTR_A10SR_PWR_GOOD3_REG: ->> + case ALTR_A10SR_FMCAB_REG: ->> + case ALTR_A10SR_HPS_RST_REG: ->> + case ALTR_A10SR_USB_QSPI_REG: ->> + case ALTR_A10SR_SFPA_REG: ->> + case ALTR_A10SR_SFPB_REG: ->> + case ALTR_A10SR_I2C_M_REG: ->> + case ALTR_A10SR_WARM_RST_REG: ->> + case ALTR_A10SR_WR_KEY_REG: ->> + case ALTR_A10SR_PMBUS_REG: ->> + return true; ->> + default: ->> + return false; ->> + } ->> +} ->> + ->> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg) ->> +{ ->> + switch (reg) { ->> + case ALTR_A10SR_LED_REG: ->> + case ALTR_A10SR_PBDSW_IRQ_REG: ->> + case ALTR_A10SR_FMCAB_REG: ->> + case ALTR_A10SR_HPS_RST_REG: ->> + case ALTR_A10SR_USB_QSPI_REG: ->> + case ALTR_A10SR_SFPA_REG: ->> + case ALTR_A10SR_SFPB_REG: ->> + case ALTR_A10SR_WARM_RST_REG: ->> + case ALTR_A10SR_WR_KEY_REG: ->> + case ALTR_A10SR_PMBUS_REG: ->> + return true; ->> + default: ->> + return false; ->> + } ->> +} ->> + ->> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg) ->> +{ ->> + switch (reg) { ->> + case ALTR_A10SR_PBDSW_REG: ->> + case ALTR_A10SR_PBDSW_IRQ_REG: ->> + case ALTR_A10SR_PWR_GOOD1_REG: ->> + case ALTR_A10SR_PWR_GOOD2_REG: ->> + case ALTR_A10SR_PWR_GOOD3_REG: ->> + case ALTR_A10SR_HPS_RST_REG: ->> + case ALTR_A10SR_I2C_M_REG: ->> + case ALTR_A10SR_WARM_RST_REG: ->> + case ALTR_A10SR_WR_KEY_REG: ->> + case ALTR_A10SR_PMBUS_REG: ->> + return true; ->> + default: ->> + return false; ->> + } ->> +} ->> + ->> +const struct regmap_config altr_a10sr_regmap_config = { ->> + .reg_bits = 8, ->> + .val_bits = 8, ->> + ->> + .cache_type = REGCACHE_NONE, ->> + ->> + .use_single_rw = true, ->> + .read_flag_mask = 1, ->> + .write_flag_mask = 0, ->> + ->> + .max_register = ALTR_A10SR_WR_KEY_REG, ->> + .readable_reg = altr_a10sr_reg_readable, ->> + .writeable_reg = altr_a10sr_reg_writeable, ->> + .volatile_reg = altr_a10sr_reg_volatile, ->> + ->> +}; ->> + ->> +static int altr_a10sr_spi_probe(struct spi_device *spi) ->> +{ ->> + int ret; ->> + struct altr_a10sr *a10sr; ->> + ->> + a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr), ->> + GFP_KERNEL); ->> + if (!a10sr) ->> + return -ENOMEM; ->> + ->> + spi->mode = SPI_MODE_3; ->> + spi->bits_per_word = 8; ->> + spi_setup(spi); ->> + ->> + a10sr->dev = &spi->dev; ->> + ->> + spi_set_drvdata(spi, a10sr); ->> + ->> + a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config); ->> + if (IS_ERR(a10sr->regmap)) { ->> + ret = PTR_ERR(a10sr->regmap); ->> + dev_err(&spi->dev, "Failed to allocate register map: %d\n", ->> + ret); ->> + return ret; ->> + } -> -> Is this regmap used it more than one driver? -> + ++ */ ++ ++#include <linux/mfd/altera-a10sr.h> ++#include <linux/mfd/core.h> ++#include <linux/module.h> ++#include <linux/of.h> ++#include <linux/spi/spi.h> ++ ++static const struct mfd_cell altr_a10sr_subdev_info[] = { ++ { ++ .name = "altr_a10sr_gpio", ++ .of_compatible = "altr,a10sr-gpio", ++ }, ++}; ++ ++static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case ALTR_A10SR_VERSION_READ: ++ case ALTR_A10SR_LED_REG: ++ case ALTR_A10SR_PBDSW_REG: ++ case ALTR_A10SR_PBDSW_IRQ_REG: ++ case ALTR_A10SR_PWR_GOOD1_REG: ++ case ALTR_A10SR_PWR_GOOD2_REG: ++ case ALTR_A10SR_PWR_GOOD3_REG: ++ case ALTR_A10SR_FMCAB_REG: ++ case ALTR_A10SR_HPS_RST_REG: ++ case ALTR_A10SR_USB_QSPI_REG: ++ case ALTR_A10SR_SFPA_REG: ++ case ALTR_A10SR_SFPB_REG: ++ case ALTR_A10SR_I2C_M_REG: ++ case ALTR_A10SR_WARM_RST_REG: ++ case ALTR_A10SR_WR_KEY_REG: ++ case ALTR_A10SR_PMBUS_REG: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case ALTR_A10SR_LED_REG: ++ case ALTR_A10SR_PBDSW_IRQ_REG: ++ case ALTR_A10SR_FMCAB_REG: ++ case ALTR_A10SR_HPS_RST_REG: ++ case ALTR_A10SR_USB_QSPI_REG: ++ case ALTR_A10SR_SFPA_REG: ++ case ALTR_A10SR_SFPB_REG: ++ case ALTR_A10SR_WARM_RST_REG: ++ case ALTR_A10SR_WR_KEY_REG: ++ case ALTR_A10SR_PMBUS_REG: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg) ++{ ++ switch (reg) { ++ case ALTR_A10SR_PBDSW_REG: ++ case ALTR_A10SR_PBDSW_IRQ_REG: ++ case ALTR_A10SR_PWR_GOOD1_REG: ++ case ALTR_A10SR_PWR_GOOD2_REG: ++ case ALTR_A10SR_PWR_GOOD3_REG: ++ case ALTR_A10SR_HPS_RST_REG: ++ case ALTR_A10SR_I2C_M_REG: ++ case ALTR_A10SR_WARM_RST_REG: ++ case ALTR_A10SR_WR_KEY_REG: ++ case ALTR_A10SR_PMBUS_REG: ++ return true; ++ default: ++ return false; ++ } ++} ++ ++const struct regmap_config altr_a10sr_regmap_config = { ++ .reg_bits = 8, ++ .val_bits = 8, ++ ++ .cache_type = REGCACHE_NONE, ++ ++ .use_single_rw = true, ++ .read_flag_mask = 1, ++ .write_flag_mask = 0, ++ ++ .max_register = ALTR_A10SR_WR_KEY_REG, ++ .readable_reg = altr_a10sr_reg_readable, ++ .writeable_reg = altr_a10sr_reg_writeable, ++ .volatile_reg = altr_a10sr_reg_volatile, ++ ++}; ++ ++static int altr_a10sr_spi_probe(struct spi_device *spi) ++{ ++ int ret; ++ struct altr_a10sr *a10sr; ++ ++ a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr), ++ GFP_KERNEL); ++ if (!a10sr) ++ return -ENOMEM; ++ ++ spi->mode = SPI_MODE_3; ++ spi->bits_per_word = 8; ++ spi_setup(spi); ++ ++ a10sr->dev = &spi->dev; ++ ++ spi_set_drvdata(spi, a10sr); ++ ++ a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config); ++ if (IS_ERR(a10sr->regmap)) { ++ ret = PTR_ERR(a10sr->regmap); ++ dev_err(&spi->dev, "Failed to allocate register map: %d\n", ++ ret); ++ return ret; ++ } + + +Is this regmap used it more than one driver? + Yes, Currently, both the subdevices (GPIO & HWMON) use this regmap to communicate to the SPI registers. ->> + ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO, ->> + altr_a10sr_subdev_info, ->> + ARRAY_SIZE(altr_a10sr_subdev_info), ->> + NULL, 0, NULL); ->> + if (ret) ->> + dev_err(a10sr->dev, "Failed to register sub-devices: %d\n", ->> + ret); ->> + ->> + return ret; ->> +} ->> + ->> +static int altr_a10sr_spi_remove(struct spi_device *spi) ->> +{ ->> + mfd_remove_devices(&spi->dev); ->> + ->> + return 0; ->> +} -> -> Use devm_mfd_add_devices() and remove this function. -> + + ++ ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO, ++ altr_a10sr_subdev_info, ++ ARRAY_SIZE(altr_a10sr_subdev_info), ++ NULL, 0, NULL); ++ if (ret) ++ dev_err(a10sr->dev, "Failed to register sub-devices: %d\n", ++ ret); ++ ++ return ret; ++} ++ ++static int altr_a10sr_spi_remove(struct spi_device *spi) ++{ ++ mfd_remove_devices(&spi->dev); ++ ++ return 0; ++} + + +Use devm_mfd_add_devices() and remove this function. + + OK. ->> +static const struct of_device_id altr_a10sr_spi_of_match[] = { ->> + { .compatible = "altr,a10sr" }, ->> + { }, ->> +}; ->> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match); ->> + ->> +static struct spi_driver altr_a10sr_spi_driver = { ->> + .probe = altr_a10sr_spi_probe, ->> + .remove = altr_a10sr_spi_remove, -> -> Remove .remove. -> ->> + .driver = { ->> + .name = "altr_a10sr", ->> + .of_match_table = of_match_ptr(altr_a10sr_spi_of_match), ->> + }, ->> +}; ->> + ->> +module_spi_driver(altr_a10sr_spi_driver); ->> + ->> +MODULE_LICENSE("GPL v2"); ->> +MODULE_AUTHOR("Thor Thayer <tthayer@opensource.altera.com>"); ->> +MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver"); ->> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h ->> new file mode 100644 ->> index 0000000..c869fe7 ->> --- /dev/null ->> +++ b/include/linux/mfd/altera-a10sr.h ->> @@ -0,0 +1,87 @@ ->> +/* ->> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved ->> + * ->> + * This program is free software; you can redistribute it and/or modify it ->> + * under the terms and conditions of the GNU General Public License, ->> + * version 2, as published by the Free Software Foundation. ->> + * ->> + * This program is distributed in the hope it will be useful, but WITHOUT ->> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ->> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ->> + * more details. ->> + * ->> + * You should have received a copy of the GNU General Public License along with ->> + * this program. If not, see <http://www.gnu.org/licenses/>. ->> + * ->> + * Declarations for Altera Arria10 MAX5 System Resource Chip ->> + * ->> + * Adapted from DA9052 ->> + * Copyright(c) 2011 Dialog Semiconductor Ltd. ->> + * Author: David Dajun Chen <dchen@diasemi.com> -> -> Remove these two lines. -> + ++static const struct of_device_id altr_a10sr_spi_of_match[] = { ++ { .compatible = "altr,a10sr" }, ++ { }, ++}; ++MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match); ++ ++static struct spi_driver altr_a10sr_spi_driver = { ++ .probe = altr_a10sr_spi_probe, ++ .remove = altr_a10sr_spi_remove, + + +Remove .remove. + + ++ .driver = { ++ .name = "altr_a10sr", ++ .of_match_table = of_match_ptr(altr_a10sr_spi_of_match), ++ }, ++}; ++ ++module_spi_driver(altr_a10sr_spi_driver); ++ ++MODULE_LICENSE("GPL v2"); ++MODULE_AUTHOR("Thor Thayer <ttha...@opensource.altera.com>"); ++MODULE_DESCRIPTION("Altera Arria10 DevKit System Resource MFD Driver"); +diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h +new file mode 100644 +index 0000000..c869fe7 +--- /dev/null ++++ b/include/linux/mfd/altera-a10sr.h +@@ -0,0 +1,87 @@ ++/* ++ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms and conditions of the GNU General Public License, ++ * version 2, as published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for ++ * more details. ++ * ++ * You should have received a copy of the GNU General Public License along with ++ * this program. If not, see <http://www.gnu.org/licenses/>. ++ * ++ * Declarations for Altera Arria10 MAX5 System Resource Chip ++ * ++ * Adapted from DA9052 ++ * Copyright(c) 2011 Dialog Semiconductor Ltd. ++ * Author: David Dajun Chen <dc...@diasemi.com> + + +Remove these two lines. + + Will do. Thanks for reviewing! ->> + */ ->> + ->> +#ifndef __MFD_ALTERA_A10SR_H ->> +#define __MFD_ALTERA_A10SR_H ->> + ->> +#include <linux/completion.h> ->> +#include <linux/list.h> ->> +#include <linux/mfd/core.h> ->> +#include <linux/regmap.h> ->> +#include <linux/slab.h> ->> + ->> +/* Write registers are always on even addresses */ ->> +#define WRITE_REG_MASK 0xFE ->> +/* Odd registers are always on odd addresses */ ->> +#define READ_REG_MASK 0x01 ->> + ->> +#define ALTR_A10SR_BITS_PER_REGISTER 8 ->> +/* ->> + * To find the correct register, we divide the input GPIO by ->> + * the number of GPIO in each register. We then need to multiply ->> + * by 2 because the reads are at odd addresses. ->> + */ ->> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) ->> +#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) ->> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) ->> +#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) ->> + ->> +/* Arria10 System Controller Register Defines */ ->> +#define ALTR_A10SR_NOP 0x00 /* No Change */ ->> +#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ ->> + ->> +#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ ->> +/* LED register Bit Definitions */ ->> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ ->> +#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT ->> +#define ALTR_A10SR_OUT_VALID_RANGE_HI 7 ->> + ->> +#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */ ->> +#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */ ->> +/* Pushbutton & DIP Switch Bit Definitions */ ->> +#define ALTR_A10SR_IN_VALID_RANGE_LO 8 ->> +#define ALTR_A10SR_IN_VALID_RANGE_HI 15 ->> + ->> +#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */ ->> +#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */ ->> +#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */ ->> +#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */ ->> +#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */ ->> +#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */ ->> +#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */ ->> +#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */ ->> +#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */ ->> +#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */ ->> +#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */ ->> +#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */ ->> + ->> +/** ->> + * struct altr_a10sr - Altera Max5 MFD device private data structure ->> + * @dev: : this device ->> + * @regmap: the regmap assigned to the parent device. ->> + */ ->> +struct altr_a10sr { ->> + struct device *dev; ->> + struct regmap *regmap; ->> +}; ->> + ->> +#endif /* __MFD_ALTERA_A10SR_H */ -> + ++ */ ++ ++#ifndef __MFD_ALTERA_A10SR_H ++#define __MFD_ALTERA_A10SR_H ++ ++#include <linux/completion.h> ++#include <linux/list.h> ++#include <linux/mfd/core.h> ++#include <linux/regmap.h> ++#include <linux/slab.h> ++ ++/* Write registers are always on even addresses */ ++#define WRITE_REG_MASK 0xFE ++/* Odd registers are always on odd addresses */ ++#define READ_REG_MASK 0x01 ++ ++#define ALTR_A10SR_BITS_PER_REGISTER 8 ++/* ++ * To find the correct register, we divide the input GPIO by ++ * the number of GPIO in each register. We then need to multiply ++ * by 2 because the reads are at odd addresses. ++ */ ++#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << +1) ++#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) ++#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) ++#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) ++ ++/* Arria10 System Controller Register Defines */ ++#define ALTR_A10SR_NOP 0x00 /* No Change */ ++#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ ++ ++#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ ++/* LED register Bit Definitions */ ++#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid +*/ ++#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT ++#define ALTR_A10SR_OUT_VALID_RANGE_HI 7 ++ ++#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */ ++#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */ ++/* Pushbutton & DIP Switch Bit Definitions */ ++#define ALTR_A10SR_IN_VALID_RANGE_LO 8 ++#define ALTR_A10SR_IN_VALID_RANGE_HI 15 ++ ++#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */ ++#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */ ++#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */ ++#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */ ++#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */ ++#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */ ++#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */ ++#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */ ++#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */ ++#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */ ++#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */ ++#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */ ++ ++/** ++ * struct altr_a10sr - Altera Max5 MFD device private data structure ++ * @dev: : this device ++ * @regmap: the regmap assigned to the parent device. ++ */ ++struct altr_a10sr { ++ struct device *dev; ++ struct regmap *regmap; ++}; ++ ++#endif /* __MFD_ALTERA_A10SR_H */ + + + +-- +To unsubscribe from this list: send the line "unsubscribe linux-hwmon" in +the body of a message to majord...@vger.kernel.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 717d0fd..527706b 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,377 +1,390 @@ "ref\01461339219-15255-1-git-send-email-tthayer@opensource.altera.com\0" - "ref\01461339219-15255-4-git-send-email-tthayer@opensource.altera.com\0" - "ref\020160509160215.GF19473@dell\0" "From\0Thor Thayer <tthayer@opensource.altera.com>\0" "Subject\0Re: [PATCH 03/11] mfd: altr_a10sr: Add Altera Arria10 DevKit System Resource Chip\0" - "Date\0Mon, 9 May 2016 11:48:25 -0500\0" - "To\0Lee Jones <lee.jones@linaro.org>\0" - "Cc\0linus.walleij@linaro.org" - gnurou@gmail.com - jdelvare@suse.com - linux@roeck-us.net - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - dinguyen@opensource.altera.com - linux-gpio@vger.kernel.org - linux-hwmon@vger.kernel.org - " devicetree@vger.kernel.org\0" + "Date\0Mon, 09 May 2016 09:44:28 -0700\0" + "To\0linux-hwmon@vger.kernel.org\0" "\00:1\0" "b\0" "\n" "\n" + "\n" "On 05/09/2016 11:02 AM, Lee Jones wrote:\n" - "> On Fri, 22 Apr 2016, tthayer@opensource.altera.com wrote:\n" - ">\n" - ">> From: Thor Thayer <tthayer@opensource.altera.com>\n" - ">>\n" - ">> Add support for the Altera Arria10 Development Kit System Resource\n" - ">> chip which is implemented using a MAX5 as a external gpio extender,\n" - ">> and power supply alarm (hwmon) with the regmap framework over a SPI bus.\n" - ">>\n" - ">> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>\n" - ">> ---\n" - ">> drivers/mfd/Kconfig | 11 +++\n" - ">> drivers/mfd/Makefile | 2 +\n" - ">> drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++\n" - ">> include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++\n" - ">> 4 files changed, 279 insertions(+)\n" - ">> create mode 100644 drivers/mfd/altera-a10sr.c\n" - ">> create mode 100644 include/linux/mfd/altera-a10sr.h\n" - ">>\n" - ">> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\n" - ">> index eea61e3..4fc27c6 100644\n" - ">> --- a/drivers/mfd/Kconfig\n" - ">> +++ b/drivers/mfd/Kconfig\n" - ">> @@ -18,6 +18,17 @@ config MFD_CS5535\n" - ">> \t This is the core driver for CS5535/CS5536 MFD functions. This is\n" - ">> necessary for using the board's GPIO and MFGPT functionality.\n" - ">>\n" - ">> +config MFD_ALTERA_A10SR\n" - ">> + bool \"Altera Arria10 DevKit System Resource chip\"\n" - ">> + depends on ARCH_SOCFPGA && SPI_MASTER=y && OF\n" - ">> + select REGMAP_SPI\n" - ">> + select MFD_CORE\n" - ">> + help\n" - ">> + Support for the Altera Arria10 DevKit MAX5 System Resource chip\n" - ">> + using the SPI interface. This driver provides common support for\n" - ">> + accessing the external gpio extender (LEDs & buttons) and\n" - ">> + power supply alarms (hwmon).\n" - ">> +\n" - ">> config MFD_ACT8945A\n" - ">> \ttristate \"Active-semi ACT8945A\"\n" - ">> \tselect MFD_CORE\n" - ">> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\n" - ">> index 5eaa6465d..4f1ff91 100644\n" - ">> --- a/drivers/mfd/Makefile\n" - ">> +++ b/drivers/mfd/Makefile\n" - ">> @@ -203,3 +203,5 @@ intel-soc-pmic-objs\t\t:= intel_soc_pmic_core.o intel_soc_pmic_crc.o\n" - ">> intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC)\t+= intel_soc_pmic_bxtwc.o\n" - ">> obj-$(CONFIG_INTEL_SOC_PMIC)\t+= intel-soc-pmic.o\n" - ">> obj-$(CONFIG_MFD_MT6397)\t+= mt6397-core.o\n" - ">> +\n" - ">> +obj-$(CONFIG_MFD_ALTERA_A10SR)\t+= altera-a10sr.o\n" - ">> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c\n" - ">> new file mode 100644\n" - ">> index 0000000..2ff08e3\n" - ">> --- /dev/null\n" - ">> +++ b/drivers/mfd/altera-a10sr.c\n" - ">> @@ -0,0 +1,179 @@\n" - ">> +/*\n" - ">> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved\n" - ">> + *\n" - ">> + * This program is free software; you can redistribute it and/or modify it\n" - ">> + * under the terms and conditions of the GNU General Public License,\n" - ">> + * version 2, as published by the Free Software Foundation.\n" - ">> + *\n" - ">> + * This program is distributed in the hope it will be useful, but WITHOUT\n" - ">> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n" - ">> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" - ">> + * more details.\n" - ">> + *\n" - ">> + * You should have received a copy of the GNU General Public License along with\n" - ">> + * this program. If not, see <http://www.gnu.org/licenses/>.\n" - ">> + *\n" - ">> + * SPI access for Altera Arria10 MAX5 System Resource Chip\n" - ">> + *\n" - ">> + * Adapted from DA9052\n" - ">> + * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" - ">> + * Author: David Dajun Chen <dchen@diasemi.com>\n" - ">\n" - "> You don't need to carry the copyright or authorship tags over.\n" - ">\n" + "\n" + "On Fri, 22 Apr 2016, ttha...@opensource.altera.com wrote:\n" + "\n" + "\n" + "From: Thor Thayer <ttha...@opensource.altera.com>\n" + "To: linux-hwmon@vger.kernel.org\n" + "\n" + "Add support for the Altera Arria10 Development Kit System Resource\n" + "chip which is implemented using a MAX5 as a external gpio extender,\n" + "and power supply alarm (hwmon) with the regmap framework over a SPI bus.\n" + "\n" + "Signed-off-by: Thor Thayer <ttha...@opensource.altera.com>\n" + "---\n" + " drivers/mfd/Kconfig | 11 +++\n" + " drivers/mfd/Makefile | 2 +\n" + " drivers/mfd/altera-a10sr.c | 179 ++++++++++++++++++++++++++++++++++++++\n" + " include/linux/mfd/altera-a10sr.h | 87 ++++++++++++++++++\n" + " 4 files changed, 279 insertions(+)\n" + " create mode 100644 drivers/mfd/altera-a10sr.c\n" + " create mode 100644 include/linux/mfd/altera-a10sr.h\n" + "\n" + "diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\n" + "index eea61e3..4fc27c6 100644\n" + "--- a/drivers/mfd/Kconfig\n" + "+++ b/drivers/mfd/Kconfig\n" + "@@ -18,6 +18,17 @@ config MFD_CS5535\n" + " This is the core driver for CS5535/CS5536 MFD functions. This is\n" + " necessary for using the board's GPIO and MFGPT functionality.\n" + "\n" + "+config MFD_ALTERA_A10SR\n" + "+ bool \"Altera Arria10 DevKit System Resource chip\"\n" + "+ depends on ARCH_SOCFPGA && SPI_MASTER=y && OF\n" + "+ select REGMAP_SPI\n" + "+ select MFD_CORE\n" + "+ help\n" + "+ Support for the Altera Arria10 DevKit MAX5 System Resource chip\n" + "+ using the SPI interface. This driver provides common support for\n" + "+ accessing the external gpio extender (LEDs & buttons) and\n" + "+ power supply alarms (hwmon).\n" + "+\n" + " config MFD_ACT8945A\n" + " tristate \"Active-semi ACT8945A\"\n" + " select MFD_CORE\n" + "diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\n" + "index 5eaa6465d..4f1ff91 100644\n" + "--- a/drivers/mfd/Makefile\n" + "+++ b/drivers/mfd/Makefile\n" + "@@ -203,3 +203,5 @@ intel-soc-pmic-objs := intel_soc_pmic_core.o \n" + "intel_soc_pmic_crc.o\n" + " intel-soc-pmic-$(CONFIG_INTEL_PMC_IPC) += intel_soc_pmic_bxtwc.o\n" + " obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o\n" + " obj-$(CONFIG_MFD_MT6397) += mt6397-core.o\n" + "+\n" + "+obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o\n" + "diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c\n" + "new file mode 100644\n" + "index 0000000..2ff08e3\n" + "--- /dev/null\n" + "+++ b/drivers/mfd/altera-a10sr.c\n" + "@@ -0,0 +1,179 @@\n" + "+/*\n" + "+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved\n" + "+ *\n" + "+ * This program is free software; you can redistribute it and/or modify it\n" + "+ * under the terms and conditions of the GNU General Public License,\n" + "+ * version 2, as published by the Free Software Foundation.\n" + "+ *\n" + "+ * This program is distributed in the hope it will be useful, but WITHOUT\n" + "+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n" + "+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" + "+ * more details.\n" + "+ *\n" + "+ * You should have received a copy of the GNU General Public License along with\n" + "+ * this program. If not, see <http://www.gnu.org/licenses/>.\n" + "+ *\n" + "+ * SPI access for Altera Arria10 MAX5 System Resource Chip\n" + "+ *\n" + "+ * Adapted from DA9052\n" + "+ * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" + "+ * Author: David Dajun Chen <dc...@diasemi.com>\n" + "\n" + "\n" + "You don't need to carry the copyright or authorship tags over.\n" + "\n" + "\n" "OK. Thanks,\n" "\n" - ">> + */\n" - ">> +\n" - ">> +#include <linux/mfd/altera-a10sr.h>\n" - ">> +#include <linux/mfd/core.h>\n" - ">> +#include <linux/module.h>\n" - ">> +#include <linux/of.h>\n" - ">> +#include <linux/spi/spi.h>\n" - ">> +\n" - ">> +static const struct mfd_cell altr_a10sr_subdev_info[] = {\n" - ">> +\t{\n" - ">> +\t\t.name = \"altr_a10sr_gpio\",\n" - ">> +\t\t.of_compatible = \"altr,a10sr-gpio\",\n" - ">> +\t},\n" - ">> +};\n" - ">> +\n" - ">> +static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)\n" - ">> +{\n" - ">> +\tswitch (reg) {\n" - ">> +\tcase ALTR_A10SR_VERSION_READ:\n" - ">> +\tcase ALTR_A10SR_LED_REG:\n" - ">> +\tcase ALTR_A10SR_PBDSW_REG:\n" - ">> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD1_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD2_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD3_REG:\n" - ">> +\tcase ALTR_A10SR_FMCAB_REG:\n" - ">> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - ">> +\tcase ALTR_A10SR_USB_QSPI_REG:\n" - ">> +\tcase ALTR_A10SR_SFPA_REG:\n" - ">> +\tcase ALTR_A10SR_SFPB_REG:\n" - ">> +\tcase ALTR_A10SR_I2C_M_REG:\n" - ">> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - ">> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - ">> +\tcase ALTR_A10SR_PMBUS_REG:\n" - ">> +\t\treturn true;\n" - ">> +\tdefault:\n" - ">> +\t\treturn false;\n" - ">> +\t}\n" - ">> +}\n" - ">> +\n" - ">> +static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)\n" - ">> +{\n" - ">> +\tswitch (reg) {\n" - ">> +\tcase ALTR_A10SR_LED_REG:\n" - ">> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - ">> +\tcase ALTR_A10SR_FMCAB_REG:\n" - ">> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - ">> +\tcase ALTR_A10SR_USB_QSPI_REG:\n" - ">> +\tcase ALTR_A10SR_SFPA_REG:\n" - ">> +\tcase ALTR_A10SR_SFPB_REG:\n" - ">> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - ">> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - ">> +\tcase ALTR_A10SR_PMBUS_REG:\n" - ">> +\t\treturn true;\n" - ">> +\tdefault:\n" - ">> +\t\treturn false;\n" - ">> +\t}\n" - ">> +}\n" - ">> +\n" - ">> +static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)\n" - ">> +{\n" - ">> +\tswitch (reg) {\n" - ">> +\tcase ALTR_A10SR_PBDSW_REG:\n" - ">> +\tcase ALTR_A10SR_PBDSW_IRQ_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD1_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD2_REG:\n" - ">> +\tcase ALTR_A10SR_PWR_GOOD3_REG:\n" - ">> +\tcase ALTR_A10SR_HPS_RST_REG:\n" - ">> +\tcase ALTR_A10SR_I2C_M_REG:\n" - ">> +\tcase ALTR_A10SR_WARM_RST_REG:\n" - ">> +\tcase ALTR_A10SR_WR_KEY_REG:\n" - ">> +\tcase ALTR_A10SR_PMBUS_REG:\n" - ">> +\t\treturn true;\n" - ">> +\tdefault:\n" - ">> +\t\treturn false;\n" - ">> +\t}\n" - ">> +}\n" - ">> +\n" - ">> +const struct regmap_config altr_a10sr_regmap_config = {\n" - ">> +\t.reg_bits = 8,\n" - ">> +\t.val_bits = 8,\n" - ">> +\n" - ">> +\t.cache_type = REGCACHE_NONE,\n" - ">> +\n" - ">> +\t.use_single_rw = true,\n" - ">> +\t.read_flag_mask = 1,\n" - ">> +\t.write_flag_mask = 0,\n" - ">> +\n" - ">> +\t.max_register = ALTR_A10SR_WR_KEY_REG,\n" - ">> +\t.readable_reg = altr_a10sr_reg_readable,\n" - ">> +\t.writeable_reg = altr_a10sr_reg_writeable,\n" - ">> +\t.volatile_reg = altr_a10sr_reg_volatile,\n" - ">> +\n" - ">> +};\n" - ">> +\n" - ">> +static int altr_a10sr_spi_probe(struct spi_device *spi)\n" - ">> +{\n" - ">> +\tint ret;\n" - ">> +\tstruct altr_a10sr *a10sr;\n" - ">> +\n" - ">> +\ta10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),\n" - ">> +\t\t\t GFP_KERNEL);\n" - ">> +\tif (!a10sr)\n" - ">> +\t\treturn -ENOMEM;\n" - ">> +\n" - ">> +\tspi->mode = SPI_MODE_3;\n" - ">> +\tspi->bits_per_word = 8;\n" - ">> +\tspi_setup(spi);\n" - ">> +\n" - ">> +\ta10sr->dev = &spi->dev;\n" - ">> +\n" - ">> +\tspi_set_drvdata(spi, a10sr);\n" - ">> +\n" - ">> +\ta10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);\n" - ">> +\tif (IS_ERR(a10sr->regmap)) {\n" - ">> +\t\tret = PTR_ERR(a10sr->regmap);\n" - ">> +\t\tdev_err(&spi->dev, \"Failed to allocate register map: %d\\n\",\n" - ">> +\t\t\tret);\n" - ">> +\t\treturn ret;\n" - ">> +\t}\n" - ">\n" - "> Is this regmap used it more than one driver?\n" - ">\n" + "\n" + "+ */\n" + "+\n" + "+#include <linux/mfd/altera-a10sr.h>\n" + "+#include <linux/mfd/core.h>\n" + "+#include <linux/module.h>\n" + "+#include <linux/of.h>\n" + "+#include <linux/spi/spi.h>\n" + "+\n" + "+static const struct mfd_cell altr_a10sr_subdev_info[] = {\n" + "+ {\n" + "+ .name = \"altr_a10sr_gpio\",\n" + "+ .of_compatible = \"altr,a10sr-gpio\",\n" + "+ },\n" + "+};\n" + "+\n" + "+static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)\n" + "+{\n" + "+ switch (reg) {\n" + "+ case ALTR_A10SR_VERSION_READ:\n" + "+ case ALTR_A10SR_LED_REG:\n" + "+ case ALTR_A10SR_PBDSW_REG:\n" + "+ case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD1_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD2_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD3_REG:\n" + "+ case ALTR_A10SR_FMCAB_REG:\n" + "+ case ALTR_A10SR_HPS_RST_REG:\n" + "+ case ALTR_A10SR_USB_QSPI_REG:\n" + "+ case ALTR_A10SR_SFPA_REG:\n" + "+ case ALTR_A10SR_SFPB_REG:\n" + "+ case ALTR_A10SR_I2C_M_REG:\n" + "+ case ALTR_A10SR_WARM_RST_REG:\n" + "+ case ALTR_A10SR_WR_KEY_REG:\n" + "+ case ALTR_A10SR_PMBUS_REG:\n" + "+ return true;\n" + "+ default:\n" + "+ return false;\n" + "+ }\n" + "+}\n" + "+\n" + "+static bool altr_a10sr_reg_writeable(struct device *dev, unsigned int reg)\n" + "+{\n" + "+ switch (reg) {\n" + "+ case ALTR_A10SR_LED_REG:\n" + "+ case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "+ case ALTR_A10SR_FMCAB_REG:\n" + "+ case ALTR_A10SR_HPS_RST_REG:\n" + "+ case ALTR_A10SR_USB_QSPI_REG:\n" + "+ case ALTR_A10SR_SFPA_REG:\n" + "+ case ALTR_A10SR_SFPB_REG:\n" + "+ case ALTR_A10SR_WARM_RST_REG:\n" + "+ case ALTR_A10SR_WR_KEY_REG:\n" + "+ case ALTR_A10SR_PMBUS_REG:\n" + "+ return true;\n" + "+ default:\n" + "+ return false;\n" + "+ }\n" + "+}\n" + "+\n" + "+static bool altr_a10sr_reg_volatile(struct device *dev, unsigned int reg)\n" + "+{\n" + "+ switch (reg) {\n" + "+ case ALTR_A10SR_PBDSW_REG:\n" + "+ case ALTR_A10SR_PBDSW_IRQ_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD1_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD2_REG:\n" + "+ case ALTR_A10SR_PWR_GOOD3_REG:\n" + "+ case ALTR_A10SR_HPS_RST_REG:\n" + "+ case ALTR_A10SR_I2C_M_REG:\n" + "+ case ALTR_A10SR_WARM_RST_REG:\n" + "+ case ALTR_A10SR_WR_KEY_REG:\n" + "+ case ALTR_A10SR_PMBUS_REG:\n" + "+ return true;\n" + "+ default:\n" + "+ return false;\n" + "+ }\n" + "+}\n" + "+\n" + "+const struct regmap_config altr_a10sr_regmap_config = {\n" + "+ .reg_bits = 8,\n" + "+ .val_bits = 8,\n" + "+\n" + "+ .cache_type = REGCACHE_NONE,\n" + "+\n" + "+ .use_single_rw = true,\n" + "+ .read_flag_mask = 1,\n" + "+ .write_flag_mask = 0,\n" + "+\n" + "+ .max_register = ALTR_A10SR_WR_KEY_REG,\n" + "+ .readable_reg = altr_a10sr_reg_readable,\n" + "+ .writeable_reg = altr_a10sr_reg_writeable,\n" + "+ .volatile_reg = altr_a10sr_reg_volatile,\n" + "+\n" + "+};\n" + "+\n" + "+static int altr_a10sr_spi_probe(struct spi_device *spi)\n" + "+{\n" + "+ int ret;\n" + "+ struct altr_a10sr *a10sr;\n" + "+\n" + "+ a10sr = devm_kzalloc(&spi->dev, sizeof(*a10sr),\n" + "+ GFP_KERNEL);\n" + "+ if (!a10sr)\n" + "+ return -ENOMEM;\n" + "+\n" + "+ spi->mode = SPI_MODE_3;\n" + "+ spi->bits_per_word = 8;\n" + "+ spi_setup(spi);\n" + "+\n" + "+ a10sr->dev = &spi->dev;\n" + "+\n" + "+ spi_set_drvdata(spi, a10sr);\n" + "+\n" + "+ a10sr->regmap = devm_regmap_init_spi(spi, &altr_a10sr_regmap_config);\n" + "+ if (IS_ERR(a10sr->regmap)) {\n" + "+ ret = PTR_ERR(a10sr->regmap);\n" + "+ dev_err(&spi->dev, \"Failed to allocate register map: %d\\n\",\n" + "+ ret);\n" + "+ return ret;\n" + "+ }\n" + "\n" + "\n" + "Is this regmap used it more than one driver?\n" + "\n" "Yes, Currently, both the subdevices (GPIO & HWMON) use this regmap to \n" "communicate to the SPI registers.\n" "\n" - ">> +\tret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,\n" - ">> +\t\t\t altr_a10sr_subdev_info,\n" - ">> +\t\t\t ARRAY_SIZE(altr_a10sr_subdev_info),\n" - ">> +\t\t\t NULL, 0, NULL);\n" - ">> +\tif (ret)\n" - ">> +\t\tdev_err(a10sr->dev, \"Failed to register sub-devices: %d\\n\",\n" - ">> +\t\t\tret);\n" - ">> +\n" - ">> +\treturn ret;\n" - ">> +}\n" - ">> +\n" - ">> +static int altr_a10sr_spi_remove(struct spi_device *spi)\n" - ">> +{\n" - ">> +\tmfd_remove_devices(&spi->dev);\n" - ">> +\n" - ">> +\treturn 0;\n" - ">> +}\n" - ">\n" - "> Use devm_mfd_add_devices() and remove this function.\n" - ">\n" + "\n" + "\n" + "+ ret = mfd_add_devices(a10sr->dev, PLATFORM_DEVID_AUTO,\n" + "+ altr_a10sr_subdev_info,\n" + "+ ARRAY_SIZE(altr_a10sr_subdev_info),\n" + "+ NULL, 0, NULL);\n" + "+ if (ret)\n" + "+ dev_err(a10sr->dev, \"Failed to register sub-devices: %d\\n\",\n" + "+ ret);\n" + "+\n" + "+ return ret;\n" + "+}\n" + "+\n" + "+static int altr_a10sr_spi_remove(struct spi_device *spi)\n" + "+{\n" + "+ mfd_remove_devices(&spi->dev);\n" + "+\n" + "+ return 0;\n" + "+}\n" + "\n" + "\n" + "Use devm_mfd_add_devices() and remove this function.\n" + "\n" + "\n" "OK.\n" "\n" - ">> +static const struct of_device_id altr_a10sr_spi_of_match[] = {\n" - ">> +\t{ .compatible = \"altr,a10sr\" },\n" - ">> +\t{ },\n" - ">> +};\n" - ">> +MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);\n" - ">> +\n" - ">> +static struct spi_driver altr_a10sr_spi_driver = {\n" - ">> +\t.probe = altr_a10sr_spi_probe,\n" - ">> +\t.remove = altr_a10sr_spi_remove,\n" - ">\n" - "> Remove .remove.\n" - ">\n" - ">> +\t.driver = {\n" - ">> +\t\t.name = \"altr_a10sr\",\n" - ">> +\t\t.of_match_table = of_match_ptr(altr_a10sr_spi_of_match),\n" - ">> +\t},\n" - ">> +};\n" - ">> +\n" - ">> +module_spi_driver(altr_a10sr_spi_driver);\n" - ">> +\n" - ">> +MODULE_LICENSE(\"GPL v2\");\n" - ">> +MODULE_AUTHOR(\"Thor Thayer <tthayer@opensource.altera.com>\");\n" - ">> +MODULE_DESCRIPTION(\"Altera Arria10 DevKit System Resource MFD Driver\");\n" - ">> diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h\n" - ">> new file mode 100644\n" - ">> index 0000000..c869fe7\n" - ">> --- /dev/null\n" - ">> +++ b/include/linux/mfd/altera-a10sr.h\n" - ">> @@ -0,0 +1,87 @@\n" - ">> +/*\n" - ">> + * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved\n" - ">> + *\n" - ">> + * This program is free software; you can redistribute it and/or modify it\n" - ">> + * under the terms and conditions of the GNU General Public License,\n" - ">> + * version 2, as published by the Free Software Foundation.\n" - ">> + *\n" - ">> + * This program is distributed in the hope it will be useful, but WITHOUT\n" - ">> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n" - ">> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" - ">> + * more details.\n" - ">> + *\n" - ">> + * You should have received a copy of the GNU General Public License along with\n" - ">> + * this program. If not, see <http://www.gnu.org/licenses/>.\n" - ">> + *\n" - ">> + * Declarations for Altera Arria10 MAX5 System Resource Chip\n" - ">> + *\n" - ">> + * Adapted from DA9052\n" - ">> + * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" - ">> + * Author: David Dajun Chen <dchen@diasemi.com>\n" - ">\n" - "> Remove these two lines.\n" - ">\n" + "\n" + "+static const struct of_device_id altr_a10sr_spi_of_match[] = {\n" + "+ { .compatible = \"altr,a10sr\" },\n" + "+ { },\n" + "+};\n" + "+MODULE_DEVICE_TABLE(of, altr_a10sr_spi_of_match);\n" + "+\n" + "+static struct spi_driver altr_a10sr_spi_driver = {\n" + "+ .probe = altr_a10sr_spi_probe,\n" + "+ .remove = altr_a10sr_spi_remove,\n" + "\n" + "\n" + "Remove .remove.\n" + "\n" + "\n" + "+ .driver = {\n" + "+ .name = \"altr_a10sr\",\n" + "+ .of_match_table = of_match_ptr(altr_a10sr_spi_of_match),\n" + "+ },\n" + "+};\n" + "+\n" + "+module_spi_driver(altr_a10sr_spi_driver);\n" + "+\n" + "+MODULE_LICENSE(\"GPL v2\");\n" + "+MODULE_AUTHOR(\"Thor Thayer <ttha...@opensource.altera.com>\");\n" + "+MODULE_DESCRIPTION(\"Altera Arria10 DevKit System Resource MFD Driver\");\n" + "diff --git a/include/linux/mfd/altera-a10sr.h b/include/linux/mfd/altera-a10sr.h\n" + "new file mode 100644\n" + "index 0000000..c869fe7\n" + "--- /dev/null\n" + "+++ b/include/linux/mfd/altera-a10sr.h\n" + "@@ -0,0 +1,87 @@\n" + "+/*\n" + "+ * Copyright Altera Corporation (C) 2014-2016. All Rights Reserved\n" + "+ *\n" + "+ * This program is free software; you can redistribute it and/or modify it\n" + "+ * under the terms and conditions of the GNU General Public License,\n" + "+ * version 2, as published by the Free Software Foundation.\n" + "+ *\n" + "+ * This program is distributed in the hope it will be useful, but WITHOUT\n" + "+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\n" + "+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\n" + "+ * more details.\n" + "+ *\n" + "+ * You should have received a copy of the GNU General Public License along with\n" + "+ * this program. If not, see <http://www.gnu.org/licenses/>.\n" + "+ *\n" + "+ * Declarations for Altera Arria10 MAX5 System Resource Chip\n" + "+ *\n" + "+ * Adapted from DA9052\n" + "+ * Copyright(c) 2011 Dialog Semiconductor Ltd.\n" + "+ * Author: David Dajun Chen <dc...@diasemi.com>\n" + "\n" + "\n" + "Remove these two lines.\n" + "\n" + "\n" "Will do. Thanks for reviewing!\n" "\n" - ">> + */\n" - ">> +\n" - ">> +#ifndef __MFD_ALTERA_A10SR_H\n" - ">> +#define __MFD_ALTERA_A10SR_H\n" - ">> +\n" - ">> +#include <linux/completion.h>\n" - ">> +#include <linux/list.h>\n" - ">> +#include <linux/mfd/core.h>\n" - ">> +#include <linux/regmap.h>\n" - ">> +#include <linux/slab.h>\n" - ">> +\n" - ">> +/* Write registers are always on even addresses */\n" - ">> +#define WRITE_REG_MASK 0xFE\n" - ">> +/* Odd registers are always on odd addresses */\n" - ">> +#define READ_REG_MASK 0x01\n" - ">> +\n" - ">> +#define ALTR_A10SR_BITS_PER_REGISTER 8\n" - ">> +/*\n" - ">> + * To find the correct register, we divide the input GPIO by\n" - ">> + * the number of GPIO in each register. We then need to multiply\n" - ">> + * by 2 because the reads are at odd addresses.\n" - ">> + */\n" - ">> +#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1)\n" - ">> +#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER)\n" - ">> +#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))\n" - ">> +#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X))\n" - ">> +\n" - ">> +/* Arria10 System Controller Register Defines */\n" - ">> +#define ALTR_A10SR_NOP 0x00 /* No Change */\n" - ">> +#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */\n" - ">> +\n" - ">> +#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */\n" - ">> +/* LED register Bit Definitions */\n" - ">> +#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */\n" - ">> +#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT\n" - ">> +#define ALTR_A10SR_OUT_VALID_RANGE_HI 7\n" - ">> +\n" - ">> +#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */\n" - ">> +#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */\n" - ">> +/* Pushbutton & DIP Switch Bit Definitions */\n" - ">> +#define ALTR_A10SR_IN_VALID_RANGE_LO 8\n" - ">> +#define ALTR_A10SR_IN_VALID_RANGE_HI 15\n" - ">> +\n" - ">> +#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */\n" - ">> +#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */\n" - ">> +#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */\n" - ">> +#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */\n" - ">> +#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */\n" - ">> +#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */\n" - ">> +#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */\n" - ">> +#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */\n" - ">> +#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */\n" - ">> +#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */\n" - ">> +#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */\n" - ">> +#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */\n" - ">> +\n" - ">> +/**\n" - ">> + * struct altr_a10sr - Altera Max5 MFD device private data structure\n" - ">> + * @dev: : this device\n" - ">> + * @regmap: the regmap assigned to the parent device.\n" - ">> + */\n" - ">> +struct altr_a10sr {\n" - ">> +\tstruct device *dev;\n" - ">> +\tstruct regmap *regmap;\n" - ">> +};\n" - ">> +\n" - ">> +#endif /* __MFD_ALTERA_A10SR_H */\n" - > + "\n" + "+ */\n" + "+\n" + "+#ifndef __MFD_ALTERA_A10SR_H\n" + "+#define __MFD_ALTERA_A10SR_H\n" + "+\n" + "+#include <linux/completion.h>\n" + "+#include <linux/list.h>\n" + "+#include <linux/mfd/core.h>\n" + "+#include <linux/regmap.h>\n" + "+#include <linux/slab.h>\n" + "+\n" + "+/* Write registers are always on even addresses */\n" + "+#define WRITE_REG_MASK 0xFE\n" + "+/* Odd registers are always on odd addresses */\n" + "+#define READ_REG_MASK 0x01\n" + "+\n" + "+#define ALTR_A10SR_BITS_PER_REGISTER 8\n" + "+/*\n" + "+ * To find the correct register, we divide the input GPIO by\n" + "+ * the number of GPIO in each register. We then need to multiply\n" + "+ * by 2 because the reads are at odd addresses.\n" + "+ */\n" + "+#define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << \n" + "1)\n" + "+#define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER)\n" + "+#define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y))\n" + "+#define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X))\n" + "+\n" + "+/* Arria10 System Controller Register Defines */\n" + "+#define ALTR_A10SR_NOP 0x00 /* No Change */\n" + "+#define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */\n" + "+\n" + "+#define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */\n" + "+/* LED register Bit Definitions */\n" + "+#define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid \n" + "*/\n" + "+#define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT\n" + "+#define ALTR_A10SR_OUT_VALID_RANGE_HI 7\n" + "+\n" + "+#define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */\n" + "+#define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */\n" + "+/* Pushbutton & DIP Switch Bit Definitions */\n" + "+#define ALTR_A10SR_IN_VALID_RANGE_LO 8\n" + "+#define ALTR_A10SR_IN_VALID_RANGE_HI 15\n" + "+\n" + "+#define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */\n" + "+#define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */\n" + "+#define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */\n" + "+#define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */\n" + "+#define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */\n" + "+#define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */\n" + "+#define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */\n" + "+#define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */\n" + "+#define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */\n" + "+#define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */\n" + "+#define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */\n" + "+#define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */\n" + "+\n" + "+/**\n" + "+ * struct altr_a10sr - Altera Max5 MFD device private data structure\n" + "+ * @dev: : this device\n" + "+ * @regmap: the regmap assigned to the parent device.\n" + "+ */\n" + "+struct altr_a10sr {\n" + "+ struct device *dev;\n" + "+ struct regmap *regmap;\n" + "+};\n" + "+\n" + "+#endif /* __MFD_ALTERA_A10SR_H */\n" + "\n" + "\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe linux-hwmon\" in\n" + "the body of a message to majord...@vger.kernel.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -47abc31c2432f0217151c337983a509c34ff36ef1cf5c943727aa0e0068e1905 +d856a280e2447159a44912ab8b47f7b422a7b894aa2e72f82c702f614e9ccdd7
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