[PATCH v2] MIPS: Fix type and FCSR mask.

["Steven J. Hill" <Steven.Hill@caviumnetworks.com>]

The FCSR register is always 32-bits regardless if the platform is
32 or 64-bits. Change the type from 'long' to 'int' to reflect this.
The entire upper half-word of the FCSR register orginally set all
the bits to 1. Some platforms like the Octeon III simulator will
actually fault if ones are written to the reserved and/or the FPU
bits. Correct the mask to avoid this.
    
Signed-off-by: Steven J. Hill <Steven.Hill@caviumnetworks.com>
Acked-by: David Daney <ddaney@caviumnetworks.com>
---
v2: Change David to be Acked-by instead of Signed-off-by.


diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b725b71..4aa8c76 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -75,7 +75,7 @@ static inline unsigned long cpu_get_msa_id(void)
  */
 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
 {
-	unsigned long sr, mask, fcsr, fcsr0, fcsr1;
+	unsigned int sr, mask, fcsr, fcsr0, fcsr1;
 
 	fcsr = c->fpu_csr31;
 	mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
@@ -87,7 +87,7 @@ static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
 	write_32bit_cp1_register(CP1_STATUS, fcsr0);
 	fcsr0 = read_32bit_cp1_register(CP1_STATUS);
 
-	fcsr1 = fcsr | ~mask;
+	fcsr1 = fcsr | (FPU_CSR_COND | FPU_CSR_FS | FPU_CSR_CONDX);
 	write_32bit_cp1_register(CP1_STATUS, fcsr1);
 	fcsr1 = read_32bit_cp1_register(CP1_STATUS);