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[2001:4c4e:24cd:7200:f6bb:a872:344e:1a32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f464a96fdsm15887893f8f.24.2026.07.15.03.53.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 03:53:22 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Tvrtko Ursulin Subject: Re: [PATCH 07/11] drm/amdgpu/gfx6: Properly enable/disable priv_req and priv_inst interrupts Date: Wed, 15 Jul 2026 12:53:21 +0200 Message-ID: <5733138.E0xQCEvomI@timur-max> In-Reply-To: <12b8dbe8-579d-4b90-a3af-ec604710299c@ursulin.net> References: <20260713130709.34262-1-timur.kristof@gmail.com> <20260713130709.34262-8-timur.kristof@gmail.com> <12b8dbe8-579d-4b90-a3af-ec604710299c@ursulin.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAlius 15., szerda 12:19:40 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 Tvrtko Ursulin=20 wrote: > On 13/07/2026 14:07, Timur Krist=C3=B3f wrote: > > These were used without ever calling get()/put() on them. >=20 > > Implement it like on GFX7-8: > Used as in how? Are they even enabled without this change and if not > then does this patch fixes something other than being prep work for soft > reset? If you open gfx_v6_0.c and search for priv_reg or priv_inst, you can see th= at=20 the interrupts are used in the same manner as gfx7 and newer, but without=20 get() and put(). >=20 > > * Call amdgpu_irq_get() from gfx_v6_0_late_init() > > * Call amdgpu_irq_put() from gfx_v6_0_hw_fini() > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 5b570a4b5c01..1c7cd265fbca > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > > @@ -3131,6 +3131,22 @@ static int gfx_v6_0_early_init(struct > > amdgpu_ip_block *ip_block)>=20 > > return 0; > > =20 > > } > >=20 > > +static int gfx_v6_0_late_init(struct amdgpu_ip_block *ip_block) > > +{ > > + struct amdgpu_device *adev =3D ip_block->adev; > > + int r; > > + > > + r =3D amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); > > + if (r) > > + return r; > > + > > + r =3D amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); > > + if (r) > > + return r; > > + > > + return 0; > > +} > > + > >=20 > > static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) > > { > > =20 > > struct amdgpu_ring *ring; > >=20 > > @@ -3243,6 +3259,8 @@ static int gfx_v6_0_hw_fini(struct amdgpu_ip_block > > *ip_block)>=20 > > { > > =20 > > struct amdgpu_device *adev =3D ip_block->adev; > >=20 > > + amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); > > + amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); > >=20 > > gfx_v6_0_cp_enable(adev, false); > > adev->gfx.rlc.funcs->stop(adev); > > gfx_v6_0_fini_pg(adev); > >=20 > > @@ -3532,6 +3550,7 @@ static void gfx_v6_0_emit_mem_sync(struct > > amdgpu_ring *ring)>=20 > > static const struct amd_ip_funcs gfx_v6_0_ip_funcs =3D { > > =20 > > .name =3D "gfx_v6_0", > > .early_init =3D gfx_v6_0_early_init, > >=20 > > + .late_init =3D gfx_v6_0_late_init, > >=20 > > .sw_init =3D gfx_v6_0_sw_init, > > .sw_fini =3D gfx_v6_0_sw_fini, > > .hw_init =3D gfx_v6_0_hw_init,