From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Date: Thu, 19 May 2016 16:54:04 +0100 Message-ID: <573DE19C.8090704@nvidia.com> References: <1463055706-17744-1-git-send-email-ldewangan@nvidia.com> <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laxman Dewangan , thierry.reding@gmail.com, airlied@linux.ie, swarren@wwwdotorg.org Cc: linux-tegra@vger.kernel.org, gnurou@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: linux-tegra@vger.kernel.org Ck9uIDEyLzA1LzE2IDEzOjIxLCBMYXhtYW4gRGV3YW5nYW4gd3JvdGU6Cj4gVGhlIElPIHBpbnMg b2YgVGVncmEgU29DcyBhcmUgZ3JvdXBlZCBmb3IgY29tbW9uIGNvbnRyb2wgb2YgSU8KPiBpbnRl cmZhY2UgbGlrZSBzZXR0aW5nIHZvbHRhZ2Ugc2lnbmFsIGxldmVscyBhbmQgcG93ZXIgc3RhdGUg b2YKPiB0aGUgaW50ZXJmYWNlLiBUaGUgZ3JvdXAgaXMgZ2VuZXJhbGx5IHJlZmVycmVkIGFzIElP IHBhZHMuIFRoZQo+IHBvd2VyIHN0YXRlIGFuZCB2b2x0YWdlIGNvbnRyb2wgb2YgSU8gcGlucyBj YW4gYmUgZG9uZSBhdCBJTyBwYWRzCj4gbGV2ZWwuCj4gCj4gVGVncmEgZ2VuZXJhdGlvbiBTb0Mg c3VwcG9ydHMgdGhlIHBvd2VyIGRvd24gb2YgSU8gcGFkcyB3aGVuIGl0Cj4gaXMgbm90IHVzZWQg ZXZlbiBpbiB0aGUgYWN0aXZlIHN0YXRlIG9mIHN5c3RlbS4gVGhpcyBzYXZlcyBwb3dlcgo+IGZy b20gdGhhdCBJTyBpbnRlcmZhY2UuIEFsc28gaXQgc3VwcG9ydHMgbXVsdGlwbGUgdm9sdGFnZSBs ZXZlbAo+IGluIElPIHBpbnMgZm9yIGludGVyZmFjaW5nIG9uIHNvbWUgb2YgcGFkcy4gVGhlIElP IHBhZCB2b2x0YWdlIGlzCj4gYXV0b21hdGljYWxseSBkZXRlY3RlZCB0aWxsIFQxMjQsIGhlbmNl IFNXIG5lZWQgbm90IHRvIGNvbmZpZ3VyZQo+IHRoaXMuIEJ1dCBmcm9tIFQyMTAsIHRoZSBhdXRv bWF0aWNhbGx5IGRldGVjdGlvbiBsb2dpYyBoYXMgYmVlbgo+IHJlbW92ZWQsIGhlbmNlIFNXIG5l ZWQgdG8gZXhwbGljaXRseSBzZXQgdGhlIElPIHBhZCB2b2x0YWdlIGludG8KPiBJTyBwYWQgY29u ZmlndXJhdGlvbiByZWdpc3RlcnMuCj4gCj4gQWRkIHN1cHBvcnQgdG8gc2V0IHRoZSBwb3dlciBz dGF0ZXMgYW5kIHZvbHRhZ2UgbGV2ZWwgb2YgdGhlIElPIHBhZHMKPiBmcm9tIGNsaWVudCBkcml2 ZXIuIFRoZSBpbXBsZW1lbnRhdGlvbiBmb3IgdGhlIEFQSXMgYXJlIGluIGdlbmVyaWMKPiB3aGlj aCBpcyBhcHBsaWNhYmxlIGZvciBhbGwgZ2VuZXJhdGlvbiBvcyBUZWdyYSBTb0MuCj4gCj4gSU8g cGFkcyBJRCBhbmQgaW5mb3JtYXRpb24gb2YgYml0IGZpZWxkIGZvciBwb3dlciBzdGF0ZSBhbmQg dm9sdGFnZQo+IGxldmVsIGNvbnRyb2xzIGFyZSBhZGRlZCBmb3IgVGVncmExMjQsIFRlZ3JhMTMy IGFuZCBUZWdyYTIxMC4gVGhlIFNPUgo+IGRyaXZlciBpcyBtb2RpZmllZCB0byB1c2UgdGhlIG5l dyBBUElzLgo+IAo+IFNpZ25lZC1vZmYtYnk6IExheG1hbiBEZXdhbmdhbiA8bGRld2FuZ2FuQG52 aWRpYS5jb20+Cj4gCj4gLS0tCj4gQ2hhbmdlcyBmcm9tIFYxOgo+IFRoaXMgaXMgcmV3b3JrZWQg b24gZWFybGllciBwYXRoIHRvIGhhdmUgc2VwYXJhdGlvbiBiZXR3ZWVuIElPIHJhaWxzIGFuZAo+ IGlvIHBhZHMgYW5kIGFkZCBwb3dlciBzdGF0ZSBhbmQgdm9sdGFnZSBjb250cm9sIEFQSXMgaW4g c2luZ2xlIGNhbGwuCj4gCj4gQ2hhbmdlcyBmcm9tIFYyOgo+IC0gUmVtb3ZlIHRoZSB0ZWdyYV9p b19yYWlsX3Bvd2VyX29mZi9vbigpIGFwaXMgYW5kIGNoYW5nZSBjbGllbnQgKHNvcikgZHJpdmVy Cj4gdG8gdXNlIHRoZSBuZXcgQVBJcyBmb3IgSU8gcGFkIHBvd2VyLgo+IC0gUmVtb3ZlIHRoZSBU RUdSQV9JT19SQUlMXyBtYWNyb3MuCj4gCj4gQ2hhbmdlcyBmcm9tIFYzOgo+IC0gTWFrZSBhbGwg cGFkX2lkL2lvX3BhZF9pZCB0byBpZC4KPiAtIHRlZ3JhX2lvX3BhZF8gLT4gdGVncmFfaW9fcGFk cwo+IC0gZHBkX2JpdCAtPiBiaXQsIHB3cl9tYXNrL2JpdCB0byBtYXNrL2JpdC4KPiAtIFJlbmFt ZSBmdW5jdGlvbiB0byB0ZWdyYV9pb19wYWRzX3tzZXQsZ2V0fV92b2x0YWdlX2NvbmZpZwo+IC0g TWFrZSB0aGUgaW8gcGFkIHRhYmxlcyBjb21tb24gZm9yIGFsbCBTb0MuCj4gLSBNYWtlIGlvX3Bh ZHMgZW51bXMuCj4gLSBBZGQgZW51bXMgZm9yIHZvbHRhZ2UuCj4gCj4gQ2hhbmdlcyBmcm9tIFY0 Ogo+IC0gSU9fUEFELT5JT19QQURTCj4gLSBURUdSQV9JT19QQURTX1BPV0VSX1NPVVJDRV8gLT4g VEVHUkFfSU9fUEFEU19WQ09ORl8KPiAtLS0KPiAgZHJpdmVycy9ncHUvZHJtL3RlZ3JhL3Nvci5j IHwgICA4ICstCj4gIGRyaXZlcnMvc29jL3RlZ3JhL3BtYy5jICAgICB8IDIyMSArKysrKysrKysr KysrKysrKysrKysrKysrKysrKysrKysrKysrKy0tLS0tLQo+ICBpbmNsdWRlL3NvYy90ZWdyYS9w bWMuaCAgICAgfCAxMzIgKysrKysrKysrKysrKysrKysrLS0tLS0tLS0KPiAgMyBmaWxlcyBjaGFu Z2VkLCAyOTQgaW5zZXJ0aW9ucygrKSwgNjcgZGVsZXRpb25zKC0pCgpbc25pcF0KCj4gK3N0YXRp YyBpbnQgdGVncmFfaW9fcGFkc190b192b2x0YWdlX2JpdChjb25zdCBzdHJ1Y3QgdGVncmFfcG1j X3NvYyAqc29jLAo+ICsJCQkJCWVudW0gdGVncmFfaW9fcGFkcyBpZCkKPiArewo+ICsJLyogVDIx MCBvbmx5IHN1cHBvcnRzIGlvLXBhZCB2b2x0YWdlIGNvbmZpZyBiaXQgKi8KPiArCWlmIChzb2Mt PmlvX3BhZHNfc29jX21hc2sgIT0gVEVHUkFfSU9fUEFEU19UMjEwKQo+ICAJCXJldHVybiAtRUlO VkFMOwoKSWYgdGhpcyBpcyBvbmx5IHN1cHBvcnRlZCBmb3IgVGVncmEyMTAsIHNob3VsZCB0aGVz ZSB2b2x0YWdlIGZ1bmN0aW9ucwpiZSBkZXBlbmRlbnQgb24gQ09ORklHX0FSQ0hfVEVHUkFfMjEw X1NPQz8gSWYgc28sIHRoZW4gSSBhbSBhbHNvCndvbmRlcmluZyBpZiB3ZSBzaG91bGQgYm90aGVy IGhhdmluZyB0aGUgbWFzc2l2ZSBsb29rLXVwIHRhYmxlIGFuZCBqdXN0CmhhdmUgYSBzbWFsbGVy IHRhYmxlIHRvIHRyYW5zbGF0ZSB0aGUgSUQgdG8gYml0IGZvciB2b2x0YWdlIGFzIHlvdSBoYWQK aW4geW91ciBpbml0aWFsIHBhdGNoPyBTZWVtcyB0aGVyZSBhcmUgZmV3IGlvLXBhZHMgdGhhdCBz dXBwb3J0IHRoZQp2b2x0YWdlIGNvbmZpZ3VyYXRpb24uCgorI2RlZmluZSBURUdSQV9JT19SQUlM X1ZPTFRBR0UoX2lvX3JhaWwsIF9wb3MpCQlcCit7CQkJCQkJCVwKKwkuaW9fcmFpbF9pZCA9IFRF R1JBX0lPX1JBSUxfIyNfaW9fcmFpbCwJCVwKKwkuYml0X3Bvc2l0aW9uID0gX3BvcywJCQkJXAor fQorCitzdGF0aWMgc3RydWN0IHRlZ3JhX2lvX3JhaWxfdm9sdGFnZV9iaXRfaW5mbwp0ZWdyYTIx MF9pb19yYWlsX3ZvbHRhZ2VfaW5mb1tdID0geworCVRFR1JBX0lPX1JBSUxfVk9MVEFHRShTRE1N QzEsIDEyKSwKKwlURUdSQV9JT19SQUlMX1ZPTFRBR0UoU0RNTUMzLCAxMyksCisJVEVHUkFfSU9f UkFJTF9WT0xUQUdFKEFVRElPX0hWLCAxOCksCisJVEVHUkFfSU9fUkFJTF9WT0xUQUdFKERNSUMs IDIwKSwKKwlURUdSQV9JT19SQUlMX1ZPTFRBR0UoR1BJTywgMjEpLAorCVRFR1JBX0lPX1JBSUxf Vk9MVEFHRShTUElfSFYsIDIzKSwKK307CgpPdGhlcndpc2UsIGxvb2tzIGZpbmUgdG8gbWUuCgpD aGVlcnMKSm9uCgotLQpudnB1YmxpYwpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRyaS1kZXZlbEBsaXN0cy5mcmVl ZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5vcmcvbWFpbG1hbi9saXN0aW5m by9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755113AbcESPyN (ORCPT ); Thu, 19 May 2016 11:54:13 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16947 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754422AbcESPyM (ORCPT ); Thu, 19 May 2016 11:54:12 -0400 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 19 May 2016 08:52:03 -0700 From: Jon Hunter Subject: Re: [PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage To: Laxman Dewangan , , , References: <1463055706-17744-1-git-send-email-ldewangan@nvidia.com> <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> CC: , , , Message-ID: <573DE19C.8090704@nvidia.com> Date: Thu, 19 May 2016 16:54:04 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> X-Originating-IP: [10.21.132.103] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL102.nvidia.com (10.26.138.15) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/05/16 13:21, Laxman Dewangan wrote: > The IO pins of Tegra SoCs are grouped for common control of IO > interface like setting voltage signal levels and power state of > the interface. The group is generally referred as IO pads. The > power state and voltage control of IO pins can be done at IO pads > level. > > Tegra generation SoC supports the power down of IO pads when it > is not used even in the active state of system. This saves power > from that IO interface. Also it supports multiple voltage level > in IO pins for interfacing on some of pads. The IO pad voltage is > automatically detected till T124, hence SW need not to configure > this. But from T210, the automatically detection logic has been > removed, hence SW need to explicitly set the IO pad voltage into > IO pad configuration registers. > > Add support to set the power states and voltage level of the IO pads > from client driver. The implementation for the APIs are in generic > which is applicable for all generation os Tegra SoC. > > IO pads ID and information of bit field for power state and voltage > level controls are added for Tegra124, Tegra132 and Tegra210. The SOR > driver is modified to use the new APIs. > > Signed-off-by: Laxman Dewangan > > --- > Changes from V1: > This is reworked on earlier path to have separation between IO rails and > io pads and add power state and voltage control APIs in single call. > > Changes from V2: > - Remove the tegra_io_rail_power_off/on() apis and change client (sor) driver > to use the new APIs for IO pad power. > - Remove the TEGRA_IO_RAIL_ macros. > > Changes from V3: > - Make all pad_id/io_pad_id to id. > - tegra_io_pad_ -> tegra_io_pads > - dpd_bit -> bit, pwr_mask/bit to mask/bit. > - Rename function to tegra_io_pads_{set,get}_voltage_config > - Make the io pad tables common for all SoC. > - Make io_pads enums. > - Add enums for voltage. > > Changes from V4: > - IO_PAD->IO_PADS > - TEGRA_IO_PADS_POWER_SOURCE_ -> TEGRA_IO_PADS_VCONF_ > --- > drivers/gpu/drm/tegra/sor.c | 8 +- > drivers/soc/tegra/pmc.c | 221 ++++++++++++++++++++++++++++++++++++++------ > include/soc/tegra/pmc.h | 132 ++++++++++++++++++-------- > 3 files changed, 294 insertions(+), 67 deletions(-) [snip] > +static int tegra_io_pads_to_voltage_bit(const struct tegra_pmc_soc *soc, > + enum tegra_io_pads id) > +{ > + /* T210 only supports io-pad voltage config bit */ > + if (soc->io_pads_soc_mask != TEGRA_IO_PADS_T210) > return -EINVAL; If this is only supported for Tegra210, should these voltage functions be dependent on CONFIG_ARCH_TEGRA_210_SOC? If so, then I am also wondering if we should bother having the massive look-up table and just have a smaller table to translate the ID to bit for voltage as you had in your initial patch? Seems there are few io-pads that support the voltage configuration. +#define TEGRA_IO_RAIL_VOLTAGE(_io_rail, _pos) \ +{ \ + .io_rail_id = TEGRA_IO_RAIL_##_io_rail, \ + .bit_position = _pos, \ +} + +static struct tegra_io_rail_voltage_bit_info tegra210_io_rail_voltage_info[] = { + TEGRA_IO_RAIL_VOLTAGE(SDMMC1, 12), + TEGRA_IO_RAIL_VOLTAGE(SDMMC3, 13), + TEGRA_IO_RAIL_VOLTAGE(AUDIO_HV, 18), + TEGRA_IO_RAIL_VOLTAGE(DMIC, 20), + TEGRA_IO_RAIL_VOLTAGE(GPIO, 21), + TEGRA_IO_RAIL_VOLTAGE(SPI_HV, 23), +}; Otherwise, looks fine to me. Cheers Jon -- nvpublic