From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jon Hunter Subject: Re: [PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage Date: Fri, 20 May 2016 10:34:44 +0100 Message-ID: <573EDA34.2030708@nvidia.com> References: <1463055706-17744-1-git-send-email-ldewangan@nvidia.com> <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> <573DE19C.8090704@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <573DE19C.8090704@nvidia.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Laxman Dewangan , thierry.reding@gmail.com, airlied@linux.ie, swarren@wwwdotorg.org Cc: linux-tegra@vger.kernel.org, gnurou@gmail.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org List-Id: linux-tegra@vger.kernel.org Ck9uIDE5LzA1LzE2IDE2OjU0LCBKb24gSHVudGVyIHdyb3RlOgo+IAo+IE9uIDEyLzA1LzE2IDEz OjIxLCBMYXhtYW4gRGV3YW5nYW4gd3JvdGU6Cj4+IFRoZSBJTyBwaW5zIG9mIFRlZ3JhIFNvQ3Mg YXJlIGdyb3VwZWQgZm9yIGNvbW1vbiBjb250cm9sIG9mIElPCj4+IGludGVyZmFjZSBsaWtlIHNl dHRpbmcgdm9sdGFnZSBzaWduYWwgbGV2ZWxzIGFuZCBwb3dlciBzdGF0ZSBvZgo+PiB0aGUgaW50 ZXJmYWNlLiBUaGUgZ3JvdXAgaXMgZ2VuZXJhbGx5IHJlZmVycmVkIGFzIElPIHBhZHMuIFRoZQo+ PiBwb3dlciBzdGF0ZSBhbmQgdm9sdGFnZSBjb250cm9sIG9mIElPIHBpbnMgY2FuIGJlIGRvbmUg YXQgSU8gcGFkcwo+PiBsZXZlbC4KPj4KPj4gVGVncmEgZ2VuZXJhdGlvbiBTb0Mgc3VwcG9ydHMg dGhlIHBvd2VyIGRvd24gb2YgSU8gcGFkcyB3aGVuIGl0Cj4+IGlzIG5vdCB1c2VkIGV2ZW4gaW4g dGhlIGFjdGl2ZSBzdGF0ZSBvZiBzeXN0ZW0uIFRoaXMgc2F2ZXMgcG93ZXIKPj4gZnJvbSB0aGF0 IElPIGludGVyZmFjZS4gQWxzbyBpdCBzdXBwb3J0cyBtdWx0aXBsZSB2b2x0YWdlIGxldmVsCj4+ IGluIElPIHBpbnMgZm9yIGludGVyZmFjaW5nIG9uIHNvbWUgb2YgcGFkcy4gVGhlIElPIHBhZCB2 b2x0YWdlIGlzCj4+IGF1dG9tYXRpY2FsbHkgZGV0ZWN0ZWQgdGlsbCBUMTI0LCBoZW5jZSBTVyBu ZWVkIG5vdCB0byBjb25maWd1cmUKPj4gdGhpcy4gQnV0IGZyb20gVDIxMCwgdGhlIGF1dG9tYXRp Y2FsbHkgZGV0ZWN0aW9uIGxvZ2ljIGhhcyBiZWVuCj4+IHJlbW92ZWQsIGhlbmNlIFNXIG5lZWQg dG8gZXhwbGljaXRseSBzZXQgdGhlIElPIHBhZCB2b2x0YWdlIGludG8KPj4gSU8gcGFkIGNvbmZp Z3VyYXRpb24gcmVnaXN0ZXJzLgo+Pgo+PiBBZGQgc3VwcG9ydCB0byBzZXQgdGhlIHBvd2VyIHN0 YXRlcyBhbmQgdm9sdGFnZSBsZXZlbCBvZiB0aGUgSU8gcGFkcwo+PiBmcm9tIGNsaWVudCBkcml2 ZXIuIFRoZSBpbXBsZW1lbnRhdGlvbiBmb3IgdGhlIEFQSXMgYXJlIGluIGdlbmVyaWMKPj4gd2hp Y2ggaXMgYXBwbGljYWJsZSBmb3IgYWxsIGdlbmVyYXRpb24gb3MgVGVncmEgU29DLgo+Pgo+PiBJ TyBwYWRzIElEIGFuZCBpbmZvcm1hdGlvbiBvZiBiaXQgZmllbGQgZm9yIHBvd2VyIHN0YXRlIGFu ZCB2b2x0YWdlCj4+IGxldmVsIGNvbnRyb2xzIGFyZSBhZGRlZCBmb3IgVGVncmExMjQsIFRlZ3Jh MTMyIGFuZCBUZWdyYTIxMC4gVGhlIFNPUgo+PiBkcml2ZXIgaXMgbW9kaWZpZWQgdG8gdXNlIHRo ZSBuZXcgQVBJcy4KPj4KPj4gU2lnbmVkLW9mZi1ieTogTGF4bWFuIERld2FuZ2FuIDxsZGV3YW5n YW5AbnZpZGlhLmNvbT4KPj4KPj4gLS0tCj4+IENoYW5nZXMgZnJvbSBWMToKPj4gVGhpcyBpcyBy ZXdvcmtlZCBvbiBlYXJsaWVyIHBhdGggdG8gaGF2ZSBzZXBhcmF0aW9uIGJldHdlZW4gSU8gcmFp bHMgYW5kCj4+IGlvIHBhZHMgYW5kIGFkZCBwb3dlciBzdGF0ZSBhbmQgdm9sdGFnZSBjb250cm9s IEFQSXMgaW4gc2luZ2xlIGNhbGwuCj4+Cj4+IENoYW5nZXMgZnJvbSBWMjoKPj4gLSBSZW1vdmUg dGhlIHRlZ3JhX2lvX3JhaWxfcG93ZXJfb2ZmL29uKCkgYXBpcyBhbmQgY2hhbmdlIGNsaWVudCAo c29yKSBkcml2ZXIKPj4gdG8gdXNlIHRoZSBuZXcgQVBJcyBmb3IgSU8gcGFkIHBvd2VyLgo+PiAt IFJlbW92ZSB0aGUgVEVHUkFfSU9fUkFJTF8gbWFjcm9zLgo+Pgo+PiBDaGFuZ2VzIGZyb20gVjM6 Cj4+IC0gTWFrZSBhbGwgcGFkX2lkL2lvX3BhZF9pZCB0byBpZC4KPj4gLSB0ZWdyYV9pb19wYWRf IC0+IHRlZ3JhX2lvX3BhZHMKPj4gLSBkcGRfYml0IC0+IGJpdCwgcHdyX21hc2svYml0IHRvIG1h c2svYml0Lgo+PiAtIFJlbmFtZSBmdW5jdGlvbiB0byB0ZWdyYV9pb19wYWRzX3tzZXQsZ2V0fV92 b2x0YWdlX2NvbmZpZwo+PiAtIE1ha2UgdGhlIGlvIHBhZCB0YWJsZXMgY29tbW9uIGZvciBhbGwg U29DLgo+PiAtIE1ha2UgaW9fcGFkcyBlbnVtcy4KPj4gLSBBZGQgZW51bXMgZm9yIHZvbHRhZ2Uu Cj4+Cj4+IENoYW5nZXMgZnJvbSBWNDoKPj4gLSBJT19QQUQtPklPX1BBRFMKPj4gLSBURUdSQV9J T19QQURTX1BPV0VSX1NPVVJDRV8gLT4gVEVHUkFfSU9fUEFEU19WQ09ORl8KPj4gLS0tCj4+ICBk cml2ZXJzL2dwdS9kcm0vdGVncmEvc29yLmMgfCAgIDggKy0KPj4gIGRyaXZlcnMvc29jL3RlZ3Jh L3BtYy5jICAgICB8IDIyMSArKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKy0t LS0tLQo+PiAgaW5jbHVkZS9zb2MvdGVncmEvcG1jLmggICAgIHwgMTMyICsrKysrKysrKysrKysr KysrKy0tLS0tLS0tCj4+ICAzIGZpbGVzIGNoYW5nZWQsIDI5NCBpbnNlcnRpb25zKCspLCA2NyBk ZWxldGlvbnMoLSkKPiAKPiBbc25pcF0KPiAKPj4gK3N0YXRpYyBpbnQgdGVncmFfaW9fcGFkc190 b192b2x0YWdlX2JpdChjb25zdCBzdHJ1Y3QgdGVncmFfcG1jX3NvYyAqc29jLAo+PiArCQkJCQll bnVtIHRlZ3JhX2lvX3BhZHMgaWQpCj4+ICt7Cj4+ICsJLyogVDIxMCBvbmx5IHN1cHBvcnRzIGlv LXBhZCB2b2x0YWdlIGNvbmZpZyBiaXQgKi8KPj4gKwlpZiAoc29jLT5pb19wYWRzX3NvY19tYXNr ICE9IFRFR1JBX0lPX1BBRFNfVDIxMCkKPj4gIAkJcmV0dXJuIC1FSU5WQUw7Cj4gCj4gSWYgdGhp cyBpcyBvbmx5IHN1cHBvcnRlZCBmb3IgVGVncmEyMTAsIHNob3VsZCB0aGVzZSB2b2x0YWdlIGZ1 bmN0aW9ucwo+IGJlIGRlcGVuZGVudCBvbiBDT05GSUdfQVJDSF9URUdSQV8yMTBfU09DPyBJZiBz bywgdGhlbiBJIGFtIGFsc28KPiB3b25kZXJpbmcgaWYgd2Ugc2hvdWxkIGJvdGhlciBoYXZpbmcg dGhlIG1hc3NpdmUgbG9vay11cCB0YWJsZSBhbmQganVzdAo+IGhhdmUgYSBzbWFsbGVyIHRhYmxl IHRvIHRyYW5zbGF0ZSB0aGUgSUQgdG8gYml0IGZvciB2b2x0YWdlIGFzIHlvdSBoYWQKPiBpbiB5 b3VyIGluaXRpYWwgcGF0Y2g/IFNlZW1zIHRoZXJlIGFyZSBmZXcgaW8tcGFkcyB0aGF0IHN1cHBv cnQgdGhlCj4gdm9sdGFnZSBjb25maWd1cmF0aW9uLgo+IAo+ICsjZGVmaW5lIFRFR1JBX0lPX1JB SUxfVk9MVEFHRShfaW9fcmFpbCwgX3BvcykJCVwKPiArewkJCQkJCQlcCj4gKwkuaW9fcmFpbF9p ZCA9IFRFR1JBX0lPX1JBSUxfIyNfaW9fcmFpbCwJCVwKPiArCS5iaXRfcG9zaXRpb24gPSBfcG9z LAkJCQlcCj4gK30KPiArCj4gK3N0YXRpYyBzdHJ1Y3QgdGVncmFfaW9fcmFpbF92b2x0YWdlX2Jp dF9pbmZvCj4gdGVncmEyMTBfaW9fcmFpbF92b2x0YWdlX2luZm9bXSA9IHsKPiArCVRFR1JBX0lP X1JBSUxfVk9MVEFHRShTRE1NQzEsIDEyKSwKPiArCVRFR1JBX0lPX1JBSUxfVk9MVEFHRShTRE1N QzMsIDEzKSwKPiArCVRFR1JBX0lPX1JBSUxfVk9MVEFHRShBVURJT19IViwgMTgpLAo+ICsJVEVH UkFfSU9fUkFJTF9WT0xUQUdFKERNSUMsIDIwKSwKPiArCVRFR1JBX0lPX1JBSUxfVk9MVEFHRShH UElPLCAyMSksCj4gKwlURUdSQV9JT19SQUlMX1ZPTFRBR0UoU1BJX0hWLCAyMyksCj4gK307CgpT b3JyeSwgSSBmb3Jnb3QgdGhhdCB3ZSBuZWVkIHRoZSBiaWcgbG9vay11cCB0YWJsZSB0byBkZXRl cm1pbmUgaWYgdGhlCkRQRCBiaXRzIGFyZSB2YWxpZCBmb3IgYSBnaXZlbiBTT0MgYXMgc29tZSBt aWdodCBub3QgYmUuIFNvIG1heSBiZSB0aGlzCnNtYWxsZXIgbWFwcGluZyB0YWJsZSBpcyBub3Qg c3VmZmljaWVudCBhZnRlciBhbGwuCgpKb24KCi0tIApudnB1YmxpYwpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpkcmktZGV2ZWwgbWFpbGluZyBsaXN0CmRy aS1kZXZlbEBsaXN0cy5mcmVlZGVza3RvcC5vcmcKaHR0cHM6Ly9saXN0cy5mcmVlZGVza3RvcC5v cmcvbWFpbG1hbi9saXN0aW5mby9kcmktZGV2ZWwK From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933379AbcETJey (ORCPT ); Fri, 20 May 2016 05:34:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:2227 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932838AbcETJew (ORCPT ); Fri, 20 May 2016 05:34:52 -0400 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 20 May 2016 02:33:32 -0700 Subject: Re: [PATCH V5 3/3] soc/tegra: pmc: Add support for IO pads power state and voltage To: Laxman Dewangan , , , References: <1463055706-17744-1-git-send-email-ldewangan@nvidia.com> <1463055706-17744-4-git-send-email-ldewangan@nvidia.com> <573DE19C.8090704@nvidia.com> CC: , , , From: Jon Hunter Message-ID: <573EDA34.2030708@nvidia.com> Date: Fri, 20 May 2016 10:34:44 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.7.2 MIME-Version: 1.0 In-Reply-To: <573DE19C.8090704@nvidia.com> X-Originating-IP: [10.21.132.103] X-ClientProxiedBy: UKMAIL101.nvidia.com (10.26.138.13) To UKMAIL102.nvidia.com (10.26.138.15) Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 19/05/16 16:54, Jon Hunter wrote: > > On 12/05/16 13:21, Laxman Dewangan wrote: >> The IO pins of Tegra SoCs are grouped for common control of IO >> interface like setting voltage signal levels and power state of >> the interface. The group is generally referred as IO pads. The >> power state and voltage control of IO pins can be done at IO pads >> level. >> >> Tegra generation SoC supports the power down of IO pads when it >> is not used even in the active state of system. This saves power >> from that IO interface. Also it supports multiple voltage level >> in IO pins for interfacing on some of pads. The IO pad voltage is >> automatically detected till T124, hence SW need not to configure >> this. But from T210, the automatically detection logic has been >> removed, hence SW need to explicitly set the IO pad voltage into >> IO pad configuration registers. >> >> Add support to set the power states and voltage level of the IO pads >> from client driver. The implementation for the APIs are in generic >> which is applicable for all generation os Tegra SoC. >> >> IO pads ID and information of bit field for power state and voltage >> level controls are added for Tegra124, Tegra132 and Tegra210. The SOR >> driver is modified to use the new APIs. >> >> Signed-off-by: Laxman Dewangan >> >> --- >> Changes from V1: >> This is reworked on earlier path to have separation between IO rails and >> io pads and add power state and voltage control APIs in single call. >> >> Changes from V2: >> - Remove the tegra_io_rail_power_off/on() apis and change client (sor) driver >> to use the new APIs for IO pad power. >> - Remove the TEGRA_IO_RAIL_ macros. >> >> Changes from V3: >> - Make all pad_id/io_pad_id to id. >> - tegra_io_pad_ -> tegra_io_pads >> - dpd_bit -> bit, pwr_mask/bit to mask/bit. >> - Rename function to tegra_io_pads_{set,get}_voltage_config >> - Make the io pad tables common for all SoC. >> - Make io_pads enums. >> - Add enums for voltage. >> >> Changes from V4: >> - IO_PAD->IO_PADS >> - TEGRA_IO_PADS_POWER_SOURCE_ -> TEGRA_IO_PADS_VCONF_ >> --- >> drivers/gpu/drm/tegra/sor.c | 8 +- >> drivers/soc/tegra/pmc.c | 221 ++++++++++++++++++++++++++++++++++++++------ >> include/soc/tegra/pmc.h | 132 ++++++++++++++++++-------- >> 3 files changed, 294 insertions(+), 67 deletions(-) > > [snip] > >> +static int tegra_io_pads_to_voltage_bit(const struct tegra_pmc_soc *soc, >> + enum tegra_io_pads id) >> +{ >> + /* T210 only supports io-pad voltage config bit */ >> + if (soc->io_pads_soc_mask != TEGRA_IO_PADS_T210) >> return -EINVAL; > > If this is only supported for Tegra210, should these voltage functions > be dependent on CONFIG_ARCH_TEGRA_210_SOC? If so, then I am also > wondering if we should bother having the massive look-up table and just > have a smaller table to translate the ID to bit for voltage as you had > in your initial patch? Seems there are few io-pads that support the > voltage configuration. > > +#define TEGRA_IO_RAIL_VOLTAGE(_io_rail, _pos) \ > +{ \ > + .io_rail_id = TEGRA_IO_RAIL_##_io_rail, \ > + .bit_position = _pos, \ > +} > + > +static struct tegra_io_rail_voltage_bit_info > tegra210_io_rail_voltage_info[] = { > + TEGRA_IO_RAIL_VOLTAGE(SDMMC1, 12), > + TEGRA_IO_RAIL_VOLTAGE(SDMMC3, 13), > + TEGRA_IO_RAIL_VOLTAGE(AUDIO_HV, 18), > + TEGRA_IO_RAIL_VOLTAGE(DMIC, 20), > + TEGRA_IO_RAIL_VOLTAGE(GPIO, 21), > + TEGRA_IO_RAIL_VOLTAGE(SPI_HV, 23), > +}; Sorry, I forgot that we need the big look-up table to determine if the DPD bits are valid for a given SOC as some might not be. So may be this smaller mapping table is not sufficient after all. Jon -- nvpublic