From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shunqian Zheng Subject: Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu Date: Tue, 24 May 2016 10:31:17 +0800 Message-ID: <5743BCF5.8030607@rock-chips.com> References: <1463967439-13354-1-git-send-email-zhengsq@rock-chips.com> <1463967439-13354-5-git-send-email-zhengsq@rock-chips.com> <5742DEFE.1040902@arm.com> <20160523133500.GF4892@e104818-lin.cambridge.arm.com> Reply-To: zhengsq-TNX95d0MmH7DzftRWevZcw@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20160523133500.GF4892-M2fw3Uu6cmfZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Catalin Marinas , Robin Murphy Cc: Mark Rutland , heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org, joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Simon List-Id: iommu@lists.linux-foundation.org Q2F0YWxpbiwgUm9iaW4sCgpPbiAyMDE25bm0MDXmnIgyM+aXpSAyMTozNSwgQ2F0YWxpbiBNYXJp bmFzIHdyb3RlOgo+IE9uIE1vbiwgTWF5IDIzLCAyMDE2IGF0IDExOjQ0OjE0QU0gKzAxMDAsIFJv YmluIE11cnBoeSB3cm90ZToKPj4gT24gMjMvMDUvMTYgMDI6MzcsIFNodW5xaWFuIFpoZW5nIHdy b3RlOgo+Pj4gRnJvbTogU2ltb24gPHh4bUByb2NrLWNoaXBzLmNvbT4KPj4+Cj4+PiBTaWduZWQt b2ZmLWJ5OiBTaW1vbiA8eHhtQHJvY2stY2hpcHMuY29tPgo+Pj4gLS0tCj4+PiAgIGRyaXZlcnMv aW9tbXUvcm9ja2NoaXAtaW9tbXUuYyB8IDQgKysrKwo+Pj4gICAxIGZpbGUgY2hhbmdlZCwgNCBp bnNlcnRpb25zKCspCj4+Pgo+Pj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvaW9tbXUvcm9ja2NoaXAt aW9tbXUuYyBiL2RyaXZlcnMvaW9tbXUvcm9ja2NoaXAtaW9tbXUuYwo+Pj4gaW5kZXggMDQzZDE4 Yy4uMTc0MWI2NSAxMDA2NDQKPj4+IC0tLSBhL2RyaXZlcnMvaW9tbXUvcm9ja2NoaXAtaW9tbXUu Ywo+Pj4gKysrIGIvZHJpdmVycy9pb21tdS9yb2NrY2hpcC1pb21tdS5jCj4+PiBAQCAtOTUsMTIg Kzk1LDE2IEBAIHN0cnVjdCBya19pb21tdSB7Cj4+Pgo+Pj4gICBzdGF0aWMgaW5saW5lIHZvaWQg cmtfdGFibGVfZmx1c2godTMyICp2YSwgdW5zaWduZWQgaW50IGNvdW50KQo+Pj4gICB7Cj4+PiAr I2lmIGRlZmluZWQoQ09ORklHX0FSTSkKPj4+ICAgCXBoeXNfYWRkcl90IHBhX3N0YXJ0ID0gdmly dF90b19waHlzKHZhKTsKPj4+ICAgCXBoeXNfYWRkcl90IHBhX2VuZCA9IHZpcnRfdG9fcGh5cyh2 YSArIGNvdW50KTsKPj4+ICAgCXNpemVfdCBzaXplID0gcGFfZW5kIC0gcGFfc3RhcnQ7Cj4+Pgo+ Pj4gICAJX19jcHVjX2ZsdXNoX2RjYWNoZV9hcmVhKHZhLCBzaXplKTsKPj4+ICAgCW91dGVyX2Zs dXNoX3JhbmdlKHBhX3N0YXJ0LCBwYV9lbmQpOwo+Pj4gKyNlbGlmIGRlZmluZWQoQ09ORklHX0FS TTY0KQo+Pj4gKwlfX2RtYV9mbHVzaF9yYW5nZSh2YSwgdmEgKyBjb3VudCk7Cj4+PiArI2VuZGlm Cj4+IFVnaCwgcGxlYXNlIGRvbid0IHVzZSBhcmNoLXByaXZhdGUgY2FjaGUgbWFpbnRlbmFuY2Ug ZnVuY3Rpb25zIGRpcmVjdGx5IGZyb20KPj4gYSBkcml2ZXIuIEFsbG9jYXRpbmcvbWFwcGluZyBw YWdlIHRhYmxlcyB0byBiZSByZWFkIGJ5IHRoZSBJT01NVSBpcyBzdGlsbAo+PiBETUEsIHNvIHVz aW5nIHRoZSBETUEgQVBJcyBpcyB0aGUgY29ycmVjdCB3YXkgdG8gbWFuYWdlIHRoZW0sICplc3Bl Y2lhbGx5Kgo+PiBpZiBpdCBuZWVkcyB0byB3b3JrIGFjcm9zcyBtdWx0aXBsZSBhcmNoaXRlY3R1 cmVzLgpJdCdzIGVhc2llciBmb3IgdXMgaWYgY2hhbmdpbmcgIHRoZSBfX2RtYV9mbHVzaF9yYW5n ZSgpIHRvIApfX2ZsdXNoX2RjYWNoZV9hcmVhKCkgaXMgYWNjZXB0YWJsZSBoZXJlPwoKVGhhbmsg eW91LAotIHNodW5xaWFuCj4gSSBmdWxseSBhZ3JlZSwgdGhlc2UgZnVuY3Rpb25zIHNob3VsZCBu b3QgYmUgdXNlZCBpbiBkcml2ZXJzLgoKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fXwpMaW51eC1yb2NrY2hpcCBtYWlsaW5nIGxpc3QKTGludXgtcm9ja2No aXBAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFkLm9yZy9tYWlsbWFu L2xpc3RpbmZvL2xpbnV4LXJvY2tjaGlwCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754262AbcEXCd5 (ORCPT ); Mon, 23 May 2016 22:33:57 -0400 Received: from regular2.263xmail.com ([211.157.152.4]:58026 "EHLO regular2.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754041AbcEXCd4 (ORCPT ); Mon, 23 May 2016 22:33:56 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: zhengsq@rock-chips.com X-FST-TO: xxm@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: zhengsq@rock-chips.com X-UNIQUE-TAG: <312daa4a854ea87bbaa7d8ba485f69bb> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <5743BCF5.8030607@rock-chips.com> Date: Tue, 24 May 2016 10:31:17 +0800 From: Shunqian Zheng Reply-To: zhengsq@rock-chips.com User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 MIME-Version: 1.0 To: Catalin Marinas , Robin Murphy CC: joro@8bytes.org, heiko@sntech.de, Mark Rutland , linux-rockchip@lists.infradead.org, iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org, Simon Subject: Re: [PATCH 4/5] iommu/rockchip: add ARM64 cache flush operation for iommu References: <1463967439-13354-1-git-send-email-zhengsq@rock-chips.com> <1463967439-13354-5-git-send-email-zhengsq@rock-chips.com> <5742DEFE.1040902@arm.com> <20160523133500.GF4892@e104818-lin.cambridge.arm.com> In-Reply-To: <20160523133500.GF4892@e104818-lin.cambridge.arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Catalin, Robin, On 2016年05月23日 21:35, Catalin Marinas wrote: > On Mon, May 23, 2016 at 11:44:14AM +0100, Robin Murphy wrote: >> On 23/05/16 02:37, Shunqian Zheng wrote: >>> From: Simon >>> >>> Signed-off-by: Simon >>> --- >>> drivers/iommu/rockchip-iommu.c | 4 ++++ >>> 1 file changed, 4 insertions(+) >>> >>> diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c >>> index 043d18c..1741b65 100644 >>> --- a/drivers/iommu/rockchip-iommu.c >>> +++ b/drivers/iommu/rockchip-iommu.c >>> @@ -95,12 +95,16 @@ struct rk_iommu { >>> >>> static inline void rk_table_flush(u32 *va, unsigned int count) >>> { >>> +#if defined(CONFIG_ARM) >>> phys_addr_t pa_start = virt_to_phys(va); >>> phys_addr_t pa_end = virt_to_phys(va + count); >>> size_t size = pa_end - pa_start; >>> >>> __cpuc_flush_dcache_area(va, size); >>> outer_flush_range(pa_start, pa_end); >>> +#elif defined(CONFIG_ARM64) >>> + __dma_flush_range(va, va + count); >>> +#endif >> Ugh, please don't use arch-private cache maintenance functions directly from >> a driver. Allocating/mapping page tables to be read by the IOMMU is still >> DMA, so using the DMA APIs is the correct way to manage them, *especially* >> if it needs to work across multiple architectures. It's easier for us if changing the __dma_flush_range() to __flush_dcache_area() is acceptable here? Thank you, - shunqian > I fully agree, these functions should not be used in drivers.