From: Lokesh Vutla <lokeshvutla@ti.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/4] ARM: DRA7: Consolidate voltage macros across different SoCs
Date: Tue, 24 May 2016 18:03:42 +0530 [thread overview]
Message-ID: <57444A26.8080806@ti.com> (raw)
In-Reply-To: <1464028337-13426-4-git-send-email-s-anna@ti.com>
On Tuesday 24 May 2016 12:02 AM, Suman Anna wrote:
> The voltage values for each voltage domain at an OPP is identical
> across all the SoCs in the DRA7 family. The current code defines
> one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
> macros. Consolidate both these sets into a single set.
>
> This is done so as to minimize the number of macros used when voltage
> values will be added for other OPPs as well.
>
> Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Thanks and regards,
Lokesh
> ---
> arch/arm/cpu/armv7/omap5/hw_data.c | 20 ++++++++++----------
> arch/arm/include/asm/arch-omap5/clock.h | 19 ++++++-------------
> board/ti/am57xx/board.c | 10 +++++-----
> 3 files changed, 21 insertions(+), 28 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
> index 948461a..b0c83ad 100644
> --- a/arch/arm/cpu/armv7/omap5/hw_data.c
> +++ b/arch/arm/cpu/armv7/omap5/hw_data.c
> @@ -365,34 +365,34 @@ struct vcores_data omap5430_volts_es2 = {
> };
>
> struct vcores_data dra752_volts = {
> - .mpu.value = VDD_MPU_DRA752,
> + .mpu.value = VDD_MPU_DRA7,
> .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
> .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .mpu.addr = TPS659038_REG_ADDR_SMPS12,
> .mpu.pmic = &tps659038,
> .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
>
> - .eve.value = VDD_EVE_DRA752,
> + .eve.value = VDD_EVE_DRA7,
> .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
> .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .eve.addr = TPS659038_REG_ADDR_SMPS45,
> .eve.pmic = &tps659038,
> .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
>
> - .gpu.value = VDD_GPU_DRA752,
> + .gpu.value = VDD_GPU_DRA7,
> .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
> .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .gpu.addr = TPS659038_REG_ADDR_SMPS6,
> .gpu.pmic = &tps659038,
> .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
>
> - .core.value = VDD_CORE_DRA752,
> + .core.value = VDD_CORE_DRA7,
> .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
> .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .core.addr = TPS659038_REG_ADDR_SMPS7,
> .core.pmic = &tps659038,
>
> - .iva.value = VDD_IVA_DRA752,
> + .iva.value = VDD_IVA_DRA7,
> .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
> .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .iva.addr = TPS659038_REG_ADDR_SMPS8,
> @@ -401,14 +401,14 @@ struct vcores_data dra752_volts = {
> };
>
> struct vcores_data dra722_volts = {
> - .mpu.value = VDD_MPU_DRA72x,
> + .mpu.value = VDD_MPU_DRA7,
> .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
> .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .mpu.addr = TPS65917_REG_ADDR_SMPS1,
> .mpu.pmic = &tps659038,
> .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
>
> - .core.value = VDD_CORE_DRA72x,
> + .core.value = VDD_CORE_DRA7,
> .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
> .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .core.addr = TPS65917_REG_ADDR_SMPS2,
> @@ -418,21 +418,21 @@ struct vcores_data dra722_volts = {
> * The DSPEVE, GPU and IVA rails are usually grouped on DRA72x
> * designs and powered by TPS65917 SMPS3, as on the J6Eco EVM.
> */
> - .gpu.value = VDD_GPU_DRA72x,
> + .gpu.value = VDD_GPU_DRA7,
> .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
> .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .gpu.addr = TPS65917_REG_ADDR_SMPS3,
> .gpu.pmic = &tps659038,
> .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
>
> - .eve.value = VDD_EVE_DRA72x,
> + .eve.value = VDD_EVE_DRA7,
> .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
> .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .eve.addr = TPS65917_REG_ADDR_SMPS3,
> .eve.pmic = &tps659038,
> .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
>
> - .iva.value = VDD_IVA_DRA72x,
> + .iva.value = VDD_IVA_DRA7,
> .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
> .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .iva.addr = TPS65917_REG_ADDR_SMPS3,
> diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
> index a850043..8c121d6 100644
> --- a/arch/arm/include/asm/arch-omap5/clock.h
> +++ b/arch/arm/include/asm/arch-omap5/clock.h
> @@ -239,19 +239,12 @@
> #define VDD_MPU_ES2_LOW 880
> #define VDD_MM_ES2_LOW 880
>
> -/* DRA74x/75x voltage settings in mv for OPP_NOM per DM */
> -#define VDD_MPU_DRA752 1150
> -#define VDD_CORE_DRA752 1150
> -#define VDD_EVE_DRA752 1060
> -#define VDD_GPU_DRA752 1060
> -#define VDD_IVA_DRA752 1060
> -
> -/* DRA72x voltage settings in mv for OPP_NOM per DM */
> -#define VDD_MPU_DRA72x 1150
> -#define VDD_CORE_DRA72x 1150
> -#define VDD_EVE_DRA72x 1060
> -#define VDD_GPU_DRA72x 1060
> -#define VDD_IVA_DRA72x 1060
> +/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
> +#define VDD_MPU_DRA7 1150
> +#define VDD_CORE_DRA7 1150
> +#define VDD_EVE_DRA7 1060
> +#define VDD_GPU_DRA7 1060
> +#define VDD_IVA_DRA7 1060
>
> /* Efuse register offsets for DRA7xx platform */
> #define DRA752_EFUSE_BASE 0x4A002000
> diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
> index 1e978dc..a6a4ccb 100644
> --- a/board/ti/am57xx/board.c
> +++ b/board/ti/am57xx/board.c
> @@ -216,34 +216,34 @@ void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, const u32 **regs, u32 *size)
> }
>
> struct vcores_data beagle_x15_volts = {
> - .mpu.value = VDD_MPU_DRA752,
> + .mpu.value = VDD_MPU_DRA7,
> .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU,
> .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .mpu.addr = TPS659038_REG_ADDR_SMPS12,
> .mpu.pmic = &tps659038,
> .mpu.abb_tx_done_mask = OMAP_ABB_MPU_TXDONE_MASK,
>
> - .eve.value = VDD_EVE_DRA752,
> + .eve.value = VDD_EVE_DRA7,
> .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE,
> .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .eve.addr = TPS659038_REG_ADDR_SMPS45,
> .eve.pmic = &tps659038,
> .eve.abb_tx_done_mask = OMAP_ABB_EVE_TXDONE_MASK,
>
> - .gpu.value = VDD_GPU_DRA752,
> + .gpu.value = VDD_GPU_DRA7,
> .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU,
> .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .gpu.addr = TPS659038_REG_ADDR_SMPS45,
> .gpu.pmic = &tps659038,
> .gpu.abb_tx_done_mask = OMAP_ABB_GPU_TXDONE_MASK,
>
> - .core.value = VDD_CORE_DRA752,
> + .core.value = VDD_CORE_DRA7,
> .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE,
> .core.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .core.addr = TPS659038_REG_ADDR_SMPS6,
> .core.pmic = &tps659038,
>
> - .iva.value = VDD_IVA_DRA752,
> + .iva.value = VDD_IVA_DRA7,
> .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA,
> .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS,
> .iva.addr = TPS659038_REG_ADDR_SMPS45,
>
next prev parent reply other threads:[~2016-05-24 12:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-23 18:32 [U-Boot] [PATCH 0/4] DRA7 Voltage macro consolidation Suman Anna
2016-05-23 18:32 ` [U-Boot] [PATCH 1/4] ARM: DRA7: Update/Correct MPU and CORE OPP_NOM voltage values Suman Anna
2016-05-24 12:33 ` Lokesh Vutla
2016-06-03 13:58 ` [U-Boot] [U-Boot, " Tom Rini
2016-05-23 18:32 ` [U-Boot] [PATCH 2/4] ARM: DRA7: Define common macros for efuse register offsets Suman Anna
2016-05-24 12:33 ` Lokesh Vutla
2016-06-03 13:58 ` [U-Boot] [U-Boot, " Tom Rini
2016-05-23 18:32 ` [U-Boot] [PATCH 3/4] ARM: DRA7: Consolidate voltage macros across different SoCs Suman Anna
2016-05-24 12:33 ` Lokesh Vutla [this message]
2016-06-03 13:58 ` [U-Boot] [U-Boot, " Tom Rini
2016-05-23 18:32 ` [U-Boot] [PATCH 4/4] ARM: DRA7: Add macros for voltage values for all OPPs Suman Anna
2016-05-24 12:33 ` Lokesh Vutla
2016-06-03 13:58 ` [U-Boot] [U-Boot, " Tom Rini
2016-06-03 15:45 ` [U-Boot] [PATCH 0/4] DRA7 Voltage macro consolidation Suman Anna
2016-06-03 20:30 ` Tom Rini
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