diff for duplicates of <5746EB4A.4010205@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index 89a19cb..7454b33 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,51 +1,50 @@ On 18/05/16 16:29, Rhyland Klein wrote: -> From: Andrew Bresticker <abrestic@chromium.org> ->=20 +> From: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> +> > Move the UTMIPLL initialization code form clk-tegra<chip>.c files into > clk-pll.c. UTMIPLL was being configured and set in HW control right > after registration. However, when the clock init_table is processed and > child clks of PLLU are enabled, it will call in and enable PLLU as > well, and initiate SW enabling sequence even though PLLU is already in > HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status. ->=20 +> > Doing the initialization once during pllu_enable means we configure it > properly into HW control. ->=20 +> > A side effect of the commonization/localization of the UTMIPLL init > code, is that it corrects some errors that were present for earlier > generations. For instance, in clk-tegra124.c, it used to have: ->=20 +> > define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6) ->=20 +> > when the correct shift to use is present in the new version: ->=20 +> > define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27) ->=20 +> > which matches the Tegra124 TRM register definition. ->=20 -> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> ->=20 +> +> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org> +> > [rklein: Merged in some later fixes for potential deadlocks] ->=20 -> Signed-off-by: Rhyland Klein <rklein@nvidia.com> +> +> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> > --- > v4: > - Re-added examples in patch description ->=20 +> > v3: > - Flushed out description to describe this patch. ->=20 -> drivers/clk/tegra/clk-pll.c | 484 +++++++++++++++++++++++++++++++++= -++++++ +> +> drivers/clk/tegra/clk-pll.c | 484 +++++++++++++++++++++++++++++++++++++++ > drivers/clk/tegra/clk-tegra114.c | 155 +------------ > drivers/clk/tegra/clk-tegra124.c | 156 +------------ > drivers/clk/tegra/clk-tegra210.c | 182 +-------------- > drivers/clk/tegra/clk-tegra30.c | 113 +-------- > drivers/clk/tegra/clk.h | 17 ++ > 6 files changed, 510 insertions(+), 597 deletions(-) ->=20 +> > diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c > index 4e194ecc8d5e..580cae8aee6d 100644 > --- a/drivers/clk/tegra/clk-pll.c @@ -55,68 +54,68 @@ On 18/05/16 16:29, Rhyland Klein wrote: > +static int clk_pllu_enable(struct clk_hw *hw) > +{ -> + struct tegra_clk_pll *pll =3D to_clk_pll(hw); -> + struct clk_hw *pll_ref =3D clk_hw_get_parent(hw); -> + struct clk_hw *osc =3D clk_hw_get_parent(pll_ref); +> + struct tegra_clk_pll *pll = to_clk_pll(hw); +> + struct clk_hw *pll_ref = clk_hw_get_parent(hw); +> + struct clk_hw *osc = clk_hw_get_parent(pll_ref); > + unsigned long flags, input_rate; > + unsigned int i; -> + int ret =3D 0; +> + int ret = 0; > + u32 val; > + > + if (!osc) { > + pr_err("%s: failed to get OSC clock\n", __func__); > + return -EINVAL; > + } -> + input_rate =3D clk_hw_get_rate(osc); +> + input_rate = clk_hw_get_rate(osc); > + > + if (pll->lock) > + spin_lock_irqsave(pll->lock, flags); > + > + _clk_pll_enable(hw); -> + ret =3D clk_pll_wait_for_lock(pll); +> + ret = clk_pll_wait_for_lock(pll); > + if (ret < 0) > + goto out; > + -> + for (i =3D 0; i < ARRAY_SIZE(utmi_parameters); i++) { -> + if (input_rate =3D=3D utmi_parameters[i].osc_frequency) +> + for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) { +> + if (input_rate == utmi_parameters[i].osc_frequency) > + break; > + } > + -> + if (i =3D=3D ARRAY_SIZE(utmi_parameters)) { +> + if (i == ARRAY_SIZE(utmi_parameters)) { > + pr_err("%s: Unexpected input rate %lu\n", __func__, input_rate); -> + ret =3D -EINVAL; +> + ret = -EINVAL; > + goto out; > + } > + -> + val =3D pll_readl_base(pll); -> + val &=3D ~PLLU_BASE_OVERRIDE; +> + val = pll_readl_base(pll); +> + val &= ~PLLU_BASE_OVERRIDE; > + pll_writel_base(val, pll); > + -> + val =3D readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); +> + val = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2); > + /* Program UTMIP PLL stable and active counts */ -> + val &=3D ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); -> + val |=3D UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); -> + val &=3D ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); -> + val |=3D UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( +> + val &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0); +> + val |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count); +> + val &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0); +> + val |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT( > + utmi_parameters[i].active_delay_count); > + /* Remove power downs from UTMIP PLL control bits */ -> + val &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; -> + val &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; -> + val &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN; > + writel_relaxed(val, pll->clk_base + UTMIP_PLL_CFG2); > + -> + val =3D readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); +> + val = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1); > + /* Program UTMIP PLL delay and oscillator frequency counts */ -> + val &=3D ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); -> + val |=3D UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( +> + val &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0); +> + val |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT( > + utmi_parameters[i].enable_delay_count); -> + val &=3D ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); -> + val |=3D UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( +> + val &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0); +> + val |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT( > + utmi_parameters[i].xtal_freq_count); > + /* Remove power downs from UTMIP PLL control bits */ -> + val &=3D ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; -> + val &=3D ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; -> + val &=3D ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN; +> + val &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN; > + writel_relaxed(val, pll->clk_base + UTMIP_PLL_CFG1); > + > +out: @@ -132,40 +131,40 @@ In file included from include/linux/mmzone.h:7:0, from include/linux/gfp.h:5, from include/linux/slab.h:14, from drivers/clk/tegra/clk-pll.c:17: -drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_enable=92: -include/linux/spinlock.h:246:30: warning: =91flags=92 may be used +drivers/clk/tegra/clk-pll.c: In function ‘clk_pllu_enable’: +include/linux/spinlock.h:246:30: warning: ‘flags’ may be used uninitialized in this function [-Wmaybe-uninitialized] _raw_spin_unlock_irqrestore(lock, flags); \ ^ -drivers/clk/tegra/clk-pll.c:1065:16: note: =91flags=92 was declared here +drivers/clk/tegra/clk-pll.c:1065:16: note: ‘flags’ was declared here unsigned long flags, input_rate; ^ In file included from include/linux/mmzone.h:7:0, from include/linux/gfp.h:5, from include/linux/slab.h:14, from drivers/clk/tegra/clk-pll.c:17: -drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_tegra210_enable=92: -include/linux/spinlock.h:246:30: warning: =91flags=92 may be used +drivers/clk/tegra/clk-pll.c: In function ‘clk_pllu_tegra210_enable’: +include/linux/spinlock.h:246:30: warning: ‘flags’ may be used uninitialized in this function [-Wmaybe-uninitialized] _raw_spin_unlock_irqrestore(lock, flags); \ ^ -drivers/clk/tegra/clk-pll.c:2511:16: note: =91flags=92 was declared here +drivers/clk/tegra/clk-pll.c:2511:16: note: ‘flags’ was declared here unsigned long flags, input_rate; ^ In file included from include/linux/mmzone.h:7:0, from include/linux/gfp.h:5, from include/linux/slab.h:14, from drivers/clk/tegra/clk-pll.c:17: -drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_tegra114_enable=92: -include/linux/spinlock.h:246:30: warning: =91flags=92 may be used +drivers/clk/tegra/clk-pll.c: In function ‘clk_pllu_tegra114_enable’: +include/linux/spinlock.h:246:30: warning: ‘flags’ may be used uninitialized in this function [-Wmaybe-uninitialized] _raw_spin_unlock_irqrestore(lock, flags); \ ^ -drivers/clk/tegra/clk-pll.c:1677:16: note: =91flags=92 was declared here +drivers/clk/tegra/clk-pll.c:1677:16: note: ‘flags’ was declared here unsigned long flags, input_rate; Cheers Jon ---=20 +-- nvpublic diff --git a/a/content_digest b/N1/content_digest index 442d812..0f3941a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,66 +1,66 @@ "ref\01463585396-19562-1-git-send-email-rklein@nvidia.com\0" - "From\0Jon Hunter <jonathanh@nvidia.com>\0" + "ref\01463585396-19562-1-git-send-email-rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org\0" + "From\0Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" "Subject\0Re: [PATCH v4] clk: tegra: Initialize UTMIPLL when enabling PLLU\0" "Date\0Thu, 26 May 2016 13:25:46 +0100\0" - "To\0Rhyland Klein <rklein@nvidia.com>" - Thierry Reding <thierry.reding@gmail.com> - " Peter De Schrijver <pdeschrijver@nvidia.com>\0" - "Cc\0Stephen Warren <swarren@wwwdotorg.org>" - Alexandre Courbot <gnurou@gmail.com> - <linux-tegra@vger.kernel.org> - Michael Turguette <mturquette@baylibre.com> - <linux-clk@vger.kernel.org> - " Andrew Bresticker <abrestic@chromium.org>\0" + "To\0Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>" + Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + " Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" + Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> + linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + Michael Turguette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>\0" "\00:1\0" "b\0" "\n" "\n" "On 18/05/16 16:29, Rhyland Klein wrote:\n" - "> From: Andrew Bresticker <abrestic@chromium.org>\n" - ">=20\n" + "> From: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>\n" + "> \n" "> Move the UTMIPLL initialization code form clk-tegra<chip>.c files into\n" "> clk-pll.c. UTMIPLL was being configured and set in HW control right\n" "> after registration. However, when the clock init_table is processed and\n" "> child clks of PLLU are enabled, it will call in and enable PLLU as\n" "> well, and initiate SW enabling sequence even though PLLU is already in\n" "> HW control. This leads to getting UTMIPLL stuck with a SEQ_BUSY status.\n" - ">=20\n" + "> \n" "> Doing the initialization once during pllu_enable means we configure it\n" "> properly into HW control.\n" - ">=20\n" + "> \n" "> A side effect of the commonization/localization of the UTMIPLL init\n" "> code, is that it corrects some errors that were present for earlier\n" "> generations. For instance, in clk-tegra124.c, it used to have:\n" - ">=20\n" + "> \n" "> define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)\n" - ">=20\n" + "> \n" "> when the correct shift to use is present in the new version:\n" - ">=20\n" + "> \n" "> define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 27)\n" - ">=20\n" + "> \n" "> which matches the Tegra124 TRM register definition.\n" - ">=20\n" - "> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>\n" - ">=20\n" + "> \n" + "> Signed-off-by: Andrew Bresticker <abrestic-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>\n" + "> \n" "> [rklein: Merged in some later fixes for potential deadlocks]\n" - ">=20\n" - "> Signed-off-by: Rhyland Klein <rklein@nvidia.com>\n" + "> \n" + "> Signed-off-by: Rhyland Klein <rklein-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" "> ---\n" "> v4:\n" "> - Re-added examples in patch description\n" - ">=20\n" + "> \n" "> v3:\n" "> - Flushed out description to describe this patch.\n" - ">=20\n" - "> drivers/clk/tegra/clk-pll.c | 484 +++++++++++++++++++++++++++++++++=\n" - "++++++\n" + "> \n" + "> drivers/clk/tegra/clk-pll.c | 484 +++++++++++++++++++++++++++++++++++++++\n" "> drivers/clk/tegra/clk-tegra114.c | 155 +------------\n" "> drivers/clk/tegra/clk-tegra124.c | 156 +------------\n" "> drivers/clk/tegra/clk-tegra210.c | 182 +--------------\n" "> drivers/clk/tegra/clk-tegra30.c | 113 +--------\n" "> drivers/clk/tegra/clk.h | 17 ++\n" "> 6 files changed, 510 insertions(+), 597 deletions(-)\n" - ">=20\n" + "> \n" "> diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c\n" "> index 4e194ecc8d5e..580cae8aee6d 100644\n" "> --- a/drivers/clk/tegra/clk-pll.c\n" @@ -70,68 +70,68 @@ "\n" "> +static int clk_pllu_enable(struct clk_hw *hw)\n" "> +{\n" - "> +\tstruct tegra_clk_pll *pll =3D to_clk_pll(hw);\n" - "> +\tstruct clk_hw *pll_ref =3D clk_hw_get_parent(hw);\n" - "> +\tstruct clk_hw *osc =3D clk_hw_get_parent(pll_ref);\n" + "> +\tstruct tegra_clk_pll *pll = to_clk_pll(hw);\n" + "> +\tstruct clk_hw *pll_ref = clk_hw_get_parent(hw);\n" + "> +\tstruct clk_hw *osc = clk_hw_get_parent(pll_ref);\n" "> +\tunsigned long flags, input_rate;\n" "> +\tunsigned int i;\n" - "> +\tint ret =3D 0;\n" + "> +\tint ret = 0;\n" "> +\tu32 val;\n" "> +\n" "> +\tif (!osc) {\n" "> +\t\tpr_err(\"%s: failed to get OSC clock\\n\", __func__);\n" "> +\t\treturn -EINVAL;\n" "> +\t}\n" - "> +\tinput_rate =3D clk_hw_get_rate(osc);\n" + "> +\tinput_rate = clk_hw_get_rate(osc);\n" "> +\n" "> +\tif (pll->lock)\n" "> +\t\tspin_lock_irqsave(pll->lock, flags);\n" "> +\n" "> +\t_clk_pll_enable(hw);\n" - "> +\tret =3D clk_pll_wait_for_lock(pll);\n" + "> +\tret = clk_pll_wait_for_lock(pll);\n" "> +\tif (ret < 0)\n" "> +\t\tgoto out;\n" "> +\n" - "> +\tfor (i =3D 0; i < ARRAY_SIZE(utmi_parameters); i++) {\n" - "> +\t\tif (input_rate =3D=3D utmi_parameters[i].osc_frequency)\n" + "> +\tfor (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {\n" + "> +\t\tif (input_rate == utmi_parameters[i].osc_frequency)\n" "> +\t\t\tbreak;\n" "> +\t}\n" "> +\n" - "> +\tif (i =3D=3D ARRAY_SIZE(utmi_parameters)) {\n" + "> +\tif (i == ARRAY_SIZE(utmi_parameters)) {\n" "> +\t\tpr_err(\"%s: Unexpected input rate %lu\\n\", __func__, input_rate);\n" - "> +\t\tret =3D -EINVAL;\n" + "> +\t\tret = -EINVAL;\n" "> +\t\tgoto out;\n" "> +\t}\n" "> +\n" - "> +\tval =3D pll_readl_base(pll);\n" - "> +\tval &=3D ~PLLU_BASE_OVERRIDE;\n" + "> +\tval = pll_readl_base(pll);\n" + "> +\tval &= ~PLLU_BASE_OVERRIDE;\n" "> +\tpll_writel_base(val, pll);\n" "> +\n" - "> +\tval =3D readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);\n" + "> +\tval = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG2);\n" "> +\t/* Program UTMIP PLL stable and active counts */\n" - "> +\tval &=3D ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);\n" - "> +\tval |=3D UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);\n" - "> +\tval &=3D ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);\n" - "> +\tval |=3D UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(\n" + "> +\tval &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);\n" + "> +\tval |= UTMIP_PLL_CFG2_STABLE_COUNT(utmi_parameters[i].stable_count);\n" + "> +\tval &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);\n" + "> +\tval |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(\n" "> +\t\t\tutmi_parameters[i].active_delay_count);\n" "> +\t/* Remove power downs from UTMIP PLL control bits */\n" - "> +\tval &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;\n" - "> +\tval &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;\n" - "> +\tval &=3D ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;\n" "> +\twritel_relaxed(val, pll->clk_base + UTMIP_PLL_CFG2);\n" "> +\n" - "> +\tval =3D readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);\n" + "> +\tval = readl_relaxed(pll->clk_base + UTMIP_PLL_CFG1);\n" "> +\t/* Program UTMIP PLL delay and oscillator frequency counts */\n" - "> +\tval &=3D ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);\n" - "> +\tval |=3D UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(\n" + "> +\tval &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);\n" + "> +\tval |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(\n" "> +\t\tutmi_parameters[i].enable_delay_count);\n" - "> +\tval &=3D ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);\n" - "> +\tval |=3D UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(\n" + "> +\tval &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);\n" + "> +\tval |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(\n" "> +\t\tutmi_parameters[i].xtal_freq_count);\n" "> +\t/* Remove power downs from UTMIP PLL control bits */\n" - "> +\tval &=3D ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;\n" - "> +\tval &=3D ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;\n" - "> +\tval &=3D ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;\n" + "> +\tval &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;\n" "> +\twritel_relaxed(val, pll->clk_base + UTMIP_PLL_CFG1);\n" "> +\n" "> +out:\n" @@ -147,42 +147,42 @@ " from include/linux/gfp.h:5,\n" " from include/linux/slab.h:14,\n" " from drivers/clk/tegra/clk-pll.c:17:\n" - "drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_enable=92:\n" - "include/linux/spinlock.h:246:30: warning: =91flags=92 may be used\n" + "drivers/clk/tegra/clk-pll.c: In function \342\200\230clk_pllu_enable\342\200\231:\n" + "include/linux/spinlock.h:246:30: warning: \342\200\230flags\342\200\231 may be used\n" "uninitialized in this function [-Wmaybe-uninitialized]\n" " _raw_spin_unlock_irqrestore(lock, flags); \\\n" " ^\n" - "drivers/clk/tegra/clk-pll.c:1065:16: note: =91flags=92 was declared here\n" + "drivers/clk/tegra/clk-pll.c:1065:16: note: \342\200\230flags\342\200\231 was declared here\n" " unsigned long flags, input_rate;\n" " ^\n" "In file included from include/linux/mmzone.h:7:0,\n" " from include/linux/gfp.h:5,\n" " from include/linux/slab.h:14,\n" " from drivers/clk/tegra/clk-pll.c:17:\n" - "drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_tegra210_enable=92:\n" - "include/linux/spinlock.h:246:30: warning: =91flags=92 may be used\n" + "drivers/clk/tegra/clk-pll.c: In function \342\200\230clk_pllu_tegra210_enable\342\200\231:\n" + "include/linux/spinlock.h:246:30: warning: \342\200\230flags\342\200\231 may be used\n" "uninitialized in this function [-Wmaybe-uninitialized]\n" " _raw_spin_unlock_irqrestore(lock, flags); \\\n" " ^\n" - "drivers/clk/tegra/clk-pll.c:2511:16: note: =91flags=92 was declared here\n" + "drivers/clk/tegra/clk-pll.c:2511:16: note: \342\200\230flags\342\200\231 was declared here\n" " unsigned long flags, input_rate;\n" " ^\n" "In file included from include/linux/mmzone.h:7:0,\n" " from include/linux/gfp.h:5,\n" " from include/linux/slab.h:14,\n" " from drivers/clk/tegra/clk-pll.c:17:\n" - "drivers/clk/tegra/clk-pll.c: In function =91clk_pllu_tegra114_enable=92:\n" - "include/linux/spinlock.h:246:30: warning: =91flags=92 may be used\n" + "drivers/clk/tegra/clk-pll.c: In function \342\200\230clk_pllu_tegra114_enable\342\200\231:\n" + "include/linux/spinlock.h:246:30: warning: \342\200\230flags\342\200\231 may be used\n" "uninitialized in this function [-Wmaybe-uninitialized]\n" " _raw_spin_unlock_irqrestore(lock, flags); \\\n" " ^\n" - "drivers/clk/tegra/clk-pll.c:1677:16: note: =91flags=92 was declared here\n" + "drivers/clk/tegra/clk-pll.c:1677:16: note: \342\200\230flags\342\200\231 was declared here\n" " unsigned long flags, input_rate;\n" "\n" "Cheers\n" "Jon\n" "\n" - "--=20\n" + "-- \n" nvpublic -0a0ad31df79bdfdffd624cb62a11874219837d7c06aa23589ad7b50a4409b8ee +40367976deb42d25b99929b7008fa1a40ef7f8d1bf4f386b15c4dde5c5000542
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