From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48252) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6c3H-0000qa-M9 for qemu-devel@nongnu.org; Sat, 28 May 2016 07:05:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b6c3D-0001MK-GB for qemu-devel@nongnu.org; Sat, 28 May 2016 07:05:06 -0400 Received: from 11.mo6.mail-out.ovh.net ([188.165.38.119]:38927) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b6c3D-0001Lw-60 for qemu-devel@nongnu.org; Sat, 28 May 2016 07:05:03 -0400 Received: from player776.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo6.mail-out.ovh.net (Postfix) with ESMTP id 4B9F8FFC585 for ; Sat, 28 May 2016 13:04:58 +0200 (CEST) References: <1462291414-8343-1-git-send-email-clg@kaod.org> <1462291414-8343-8-git-send-email-clg@kaod.org> <20160527033832.GS17226@voom.fritz.box> <5747FDB0.4030602@kaod.org> <20160528095256.GC17226@voom.fritz.box> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <57497B49.1000100@kaod.org> Date: Sat, 28 May 2016 13:04:41 +0200 MIME-Version: 1.0 In-Reply-To: <20160528095256.GC17226@voom.fritz.box> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 07/12] ppc: Better figure out if processor has HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On 05/28/2016 11:52 AM, David Gibson wrote: > On Fri, May 27, 2016 at 09:56:32AM +0200, C=E9dric Le Goater wrote: >> On 05/27/2016 05:38 AM, David Gibson wrote: >>> On Tue, May 03, 2016 at 06:03:29PM +0200, C=E9dric Le Goater wrote: >>>> From: Benjamin Herrenschmidt >>>> >>>> We use an env. flag which is set to the initial value of MSR_HVB in >>>> the msr_mask. We also adjust the POWER8 mask to set SHV. >>>> >>>> Also use this to adjust ctx.hv so that it is *set* when the processo= r >>>> doesn't have an HV mode (970 with Apple mode for example), thus enab= ling >>>> hypervisor instructions/SPRs. >>>> >>>> Signed-off-by: Benjamin Herrenschmidt >>>> Reviewed-by: David Gibson >>>> --- >>>> target-ppc/cpu.h | 4 ++++ >>>> target-ppc/translate.c | 4 +++- >>>> target-ppc/translate_init.c | 21 ++++++++++++++++----- >>>> 3 files changed, 23 insertions(+), 6 deletions(-) >>>> >>>> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h >>>> index 2a96efcbf813..02f2e72e6d14 100644 >>>> --- a/target-ppc/cpu.h >>>> +++ b/target-ppc/cpu.h >>>> @@ -1161,6 +1161,10 @@ struct CPUPPCState { >>>> hwaddr mpic_iack; >>>> /* true when the external proxy facility mode is enabled */ >>>> bool mpic_proxy; >>>> + /* set when the processor has an HV mode, thus HV priv >>>> + * instructions and SPRs are diallowed if MSR:HV is 0 >>>> + */ >>>> + bool has_hv_mode; >>>> #endif >>>> =20 >>>> /* Those resources are used only during code translation */ >>>> diff --git a/target-ppc/translate.c b/target-ppc/translate.c >>>> index 7a672cba796d..6f55bcd34a74 100644 >>>> --- a/target-ppc/translate.c >>>> +++ b/target-ppc/translate.c >>>> @@ -11495,8 +11495,10 @@ void gen_intermediate_code(CPUPPCState *env= , struct TranslationBlock *tb) >>>> ctx.exception =3D POWERPC_EXCP_NONE; >>>> ctx.spr_cb =3D env->spr_cb; >>>> ctx.pr =3D msr_pr; >>>> - ctx.hv =3D !msr_pr && msr_hv; >>> >>> The test for msr_pr has been removed in the new version. Maybe that'= s >>> safe, but I think it needs some justification. >> >> I don't know if it is safe to run with (MSR_HV|MSR_PR) =3D 11 >=20 > Um.. I believe host userland runs routinely in that state. oui oui oui ... of course. hmm, I need to dig more the consequences of=20 the *HV* patches.=20 Thanks, C.=20 >> There is a note in the Power ISA book describing such a case but I am = not=20 >> sure qemu-ppc supports that. So I will keep the msr_pr check in the ne= xt=20 >> version : >> >> ctx.hv =3D !msr_pr && (msr_hv || !env->has_hv_mode); >=20 > Ok. >=20