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From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 2/3] MIPS: Split I & D cache line size config
Date: Tue, 31 May 2016 10:03:08 +0200	[thread overview]
Message-ID: <574D453C.9000102@gmail.com> (raw)
In-Reply-To: <20160527132806.24134-3-paul.burton@imgtec.com>



Am 27.05.2016 um 15:28 schrieb Paul Burton:
> Allow L1 Icache & L1 Dcache line size to be specified separately, since
> there's no architectural mandate that they be the same. The
> [id]cache_line_size functions are tidied up to take advantage of the
> fact that the Kconfig entries are always present to simply check them
> for zero rather than needing to #ifdef on their presence.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> 
> ---
> 
> Changes in v2:
> - Provide CONFIG_SYS_CACHELINE_SIZE as a synonym for ARCH_DMA_MINALIGN to avoid breaking drivers that use it for now.
> 
>  arch/mips/Kconfig             | 12 +++++++++---
>  arch/mips/include/asm/cache.h |  7 +++++++
>  arch/mips/lib/cache.c         | 22 +++++++---------------
>  arch/mips/lib/cache_init.S    |  4 ++--
>  board/dbau1x00/Kconfig        |  5 ++++-
>  board/micronas/vct/Kconfig    |  5 ++++-
>  board/pb1x00/Kconfig          |  5 ++++-
>  board/qca/ap121/Kconfig       |  5 ++++-
>  board/qca/ap143/Kconfig       |  5 ++++-
>  board/qemu-mips/Kconfig       |  5 ++++-
>  board/tplink/wdr4300/Kconfig  |  5 ++++-
>  11 files changed, 53 insertions(+), 27 deletions(-)
> 

applied to u-boot-mips, thanks!

-- 
- Daniel

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  reply	other threads:[~2016-05-31  8:03 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-27 13:28 [U-Boot] [PATCH v2 0/3] MIPS cache cleanups Paul Burton
2016-05-27 13:28 ` [U-Boot] [PATCH v2 1/3] MIPS: Move cache sizes to Kconfig Paul Burton
2016-05-31  8:02   ` Daniel Schwierzeck
2016-05-27 13:28 ` [U-Boot] [PATCH v2 2/3] MIPS: Split I & D cache line size config Paul Burton
2016-05-31  8:03   ` Daniel Schwierzeck [this message]
2016-05-27 13:28 ` [U-Boot] [PATCH v2 3/3] MIPS: Abstract cache op loops with a macro Paul Burton
2016-05-31  8:03   ` Daniel Schwierzeck

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