From: "Huang, Tao" <huangtao@rock-chips.com>
To: Daniel Lezcano <daniel.lezcano@linaro.org>,
Caesar Wang <wxt@rock-chips.com>,
Heiko Stuebner <heiko@sntech.de>
Cc: dianders@chromium.org, briannorris@google.com,
smbarber@google.com, linux-rockchip@lists.infradead.org,
Thomas Gleixner <tglx@linutronix.de>,
cf@rock-chips.com, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 4/5] clocksource: rockchip: add support for rk3399 SoC
Date: Wed, 1 Jun 2016 09:58:08 +0800 [thread overview]
Message-ID: <574E4130.8090600@rock-chips.com> (raw)
In-Reply-To: <574D9A66.4090209@linaro.org>
Hi Daniel:
On 2016年05月31日 22:06, Daniel Lezcano wrote:
>>
>> @@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct
>> clock_event_device *ce)
>> return rk_timer(ce)->base;
>> }
>>
>> +static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
>> +{
>> + return rk_timer(ce)->base + rk_timer(ce)->ctrl;
>
> You can do a small optimization by pre-computing 'ctrl' at init time, so
> no need to do this addition each time.
I understand what you mean, please see comment below.
And even we use ctrl as pointer, we still will get addition LDR other
then ADD.
This is disassemble code before:
0: f9408021 ldr x1, [x1,#256]
4: 52800003 mov w3, #0x0
8: 91004022 add x2, x1, #0x10
c: b9000043 str w3, [x2]
This is disassemble code after change:
0: 52800003 mov w3, #0x0
4: f9408422 ldr x2, [x1,#264]
8: b9000043 str w3, [x2]
c: f9408021 ldr x1, [x1,#256]
Of course we can assume cache hit.
>
>> +}
>> +
>> static inline void rk_timer_disable(struct clock_event_device *ce)
>> {
>> - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
>> + writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
>> }
>>
>> static inline void rk_timer_enable(struct clock_event_device *ce, u32
>> flags)
>> {
>> writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
>> - rk_base(ce) + TIMER_CONTROL_REG);
>> + rk_ctrl(ce));
>> }
>>
>> static void rk_timer_update_counter(unsigned long cycles,
>> @@ -179,4 +186,19 @@ out_unmap:
>> iounmap(bc_timer.base);
>> }
>>
>> -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);
>> +static void __init rk3288_timer_init(struct device_node *np)
>> +{
>> + bc_timer.ctrl = TIMER_CONTROL_REG3288;
>> + rk_timer_init(np);
>
> rk_timer_init(np);
> bc_timer.ctrl = bc_timer.base + TIMER_CONTROL_REG3288;
No. It's not such simple. You will access null pointer when
rk_timer_init, if we keep rk_timer_disable call in init or after
request_irq/clockevents_config_and_register and interrupt happen
immediately.
So the code maybe:
static void __init rk3288_timer_init(struct device_node *np)
{
bc_timer.base = of_iomap(np, 0);
if (!bc_timer.base) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
return;
}
bc_timer.ctrl = bc_timer.base + TIMER_CONTROL_REG3288;
rk_imter_init(np); // of course remove of_iomap from init.
Is this what you want?
WARNING: multiple messages have this Message-ID (diff)
From: huangtao@rock-chips.com (Huang, Tao)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 4/5] clocksource: rockchip: add support for rk3399 SoC
Date: Wed, 1 Jun 2016 09:58:08 +0800 [thread overview]
Message-ID: <574E4130.8090600@rock-chips.com> (raw)
In-Reply-To: <574D9A66.4090209@linaro.org>
Hi Daniel:
On 2016?05?31? 22:06, Daniel Lezcano wrote:
>>
>> @@ -46,15 +48,20 @@ static inline void __iomem *rk_base(struct
>> clock_event_device *ce)
>> return rk_timer(ce)->base;
>> }
>>
>> +static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
>> +{
>> + return rk_timer(ce)->base + rk_timer(ce)->ctrl;
>
> You can do a small optimization by pre-computing 'ctrl' at init time, so
> no need to do this addition each time.
I understand what you mean, please see comment below.
And even we use ctrl as pointer, we still will get addition LDR other
then ADD.
This is disassemble code before:
0: f9408021 ldr x1, [x1,#256]
4: 52800003 mov w3, #0x0
8: 91004022 add x2, x1, #0x10
c: b9000043 str w3, [x2]
This is disassemble code after change:
0: 52800003 mov w3, #0x0
4: f9408422 ldr x2, [x1,#264]
8: b9000043 str w3, [x2]
c: f9408021 ldr x1, [x1,#256]
Of course we can assume cache hit.
>
>> +}
>> +
>> static inline void rk_timer_disable(struct clock_event_device *ce)
>> {
>> - writel_relaxed(TIMER_DISABLE, rk_base(ce) + TIMER_CONTROL_REG);
>> + writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
>> }
>>
>> static inline void rk_timer_enable(struct clock_event_device *ce, u32
>> flags)
>> {
>> writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
>> - rk_base(ce) + TIMER_CONTROL_REG);
>> + rk_ctrl(ce));
>> }
>>
>> static void rk_timer_update_counter(unsigned long cycles,
>> @@ -179,4 +186,19 @@ out_unmap:
>> iounmap(bc_timer.base);
>> }
>>
>> -CLOCKSOURCE_OF_DECLARE(rk_timer, "rockchip,rk3288-timer", rk_timer_init);
>> +static void __init rk3288_timer_init(struct device_node *np)
>> +{
>> + bc_timer.ctrl = TIMER_CONTROL_REG3288;
>> + rk_timer_init(np);
>
> rk_timer_init(np);
> bc_timer.ctrl = bc_timer.base + TIMER_CONTROL_REG3288;
No. It's not such simple. You will access null pointer when
rk_timer_init, if we keep rk_timer_disable call in init or after
request_irq/clockevents_config_and_register and interrupt happen
immediately.
So the code maybe:
static void __init rk3288_timer_init(struct device_node *np)
{
bc_timer.base = of_iomap(np, 0);
if (!bc_timer.base) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
return;
}
bc_timer.ctrl = bc_timer.base + TIMER_CONTROL_REG3288;
rk_imter_init(np); // of course remove of_iomap from init.
Is this what you want?
next prev parent reply other threads:[~2016-06-01 1:58 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-25 9:49 [PATCH 0/5] clocksource: rockchip/timer: Support rktimer for rk3399 Caesar Wang
2016-05-25 9:49 ` Caesar Wang
2016-05-25 9:49 ` [PATCH 1/5] dt-bindings: document rk3399 rk-timer bindings Caesar Wang
2016-05-25 9:49 ` Caesar Wang
[not found] ` <1464169802-6033-2-git-send-email-wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
2016-05-25 19:11 ` Rob Herring
2016-05-25 19:11 ` Rob Herring
2016-05-25 19:11 ` Rob Herring
2016-05-25 9:49 ` [PATCH 2/5] clocksource: rockchip: remove unnecessary clear irq before request_irq Caesar Wang
2016-05-25 9:49 ` Caesar Wang
2016-05-30 23:09 ` Daniel Lezcano
2016-05-30 23:09 ` Daniel Lezcano
2016-05-31 17:03 ` Doug Anderson
2016-05-31 17:03 ` Doug Anderson
2016-06-01 2:30 ` Huang, Tao
2016-06-01 2:30 ` Huang, Tao
2016-06-01 2:36 ` Doug Anderson
2016-06-01 2:36 ` Doug Anderson
2016-05-25 9:50 ` [PATCH 3/5] clocksource: rockchip: add dynamic irq flag to the timer Caesar Wang
2016-05-25 9:50 ` Caesar Wang
2016-05-30 23:16 ` Daniel Lezcano
2016-05-30 23:16 ` Daniel Lezcano
[not found] ` <574CC9DE.1050501-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-05-31 13:45 ` Huang, Tao
2016-05-31 13:45 ` Huang, Tao
2016-05-31 13:45 ` Huang, Tao
2016-05-25 9:50 ` [PATCH 4/5] clocksource: rockchip: add support for rk3399 SoC Caesar Wang
2016-05-25 9:50 ` Caesar Wang
2016-05-30 23:28 ` Daniel Lezcano
2016-05-30 23:28 ` Daniel Lezcano
[not found] ` <574CCCB4.1030001-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-05-31 13:46 ` Huang, Tao
2016-05-31 13:46 ` Huang, Tao
2016-05-31 13:46 ` Huang, Tao
2016-05-31 14:06 ` Daniel Lezcano
2016-05-31 14:06 ` Daniel Lezcano
2016-06-01 1:58 ` Huang, Tao [this message]
2016-06-01 1:58 ` Huang, Tao
2016-06-01 6:16 ` Daniel Lezcano
2016-06-01 6:16 ` Daniel Lezcano
2016-05-25 9:50 ` [PATCH 5/5] ARM64: dts: rockchip: add rktimer device node for rk3399 Caesar Wang
2016-05-25 9:50 ` Caesar Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=574E4130.8090600@rock-chips.com \
--to=huangtao@rock-chips.com \
--cc=briannorris@google.com \
--cc=cf@rock-chips.com \
--cc=daniel.lezcano@linaro.org \
--cc=dianders@chromium.org \
--cc=heiko@sntech.de \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-rockchip@lists.infradead.org \
--cc=smbarber@google.com \
--cc=tglx@linutronix.de \
--cc=wxt@rock-chips.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.