From: York Sun <york.sun@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl
Date: Wed, 1 Jun 2016 08:49:41 -0700 [thread overview]
Message-ID: <574F0415.9090506@nxp.com> (raw)
In-Reply-To: <AMXPR04MB1849B057EF5794970A616E4F2470@AMXPR04MB184.eurprd04.prod.outlook.com>
On 05/31/2016 10:12 PM, Shengzhou Liu wrote:
>> -----Original Message-----
>> From: York Sun [mailto:york.sun at nxp.com]
>> Sent: Wednesday, June 01, 2016 12:04 AM
>> To: Shengzhou Liu <shengzhou.liu@nxp.com>; u-boot at lists.denx.de
>> Shengzhou,
>>
>> If you have to use an odd number for clk_adj, we can go ahead to merge
>> these patches. In my experience, clk_adj is very forgivable. If you have only
>> one value works, there is probably something wrong.
>>
>> York
>>
> York,
> The odd clk_adj = 9 is the optimal with timing centralization, maybe it work if set it to 8, but not the optimal.
> Theoretically we should have the actual value instead of dividing 2 to avoid confusion for customers.
> Shengzhou
>
OK. Thanks for the explanation.
York
next prev parent reply other threads:[~2016-06-01 15:49 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-04 2:20 [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl Shengzhou Liu
2016-05-04 2:20 ` [U-Boot] [PATCH 2/2] board/freescale: Update ddr clk_adjust Shengzhou Liu
2016-06-04 5:03 ` York Sun
2016-05-16 16:55 ` [U-Boot] [PATCH 1/2] drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl York Sun
2016-05-31 3:18 ` Shengzhou Liu
2016-05-31 16:03 ` York Sun
2016-06-01 5:12 ` Shengzhou Liu
2016-06-01 15:49 ` York Sun [this message]
2016-06-04 5:02 ` York Sun
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