From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40989) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8seG-0005T0-TK for qemu-devel@nongnu.org; Fri, 03 Jun 2016 13:12:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8seF-0007OE-1i for qemu-devel@nongnu.org; Fri, 03 Jun 2016 13:12:39 -0400 References: <20160603154549.GA31406@ibawizard> From: Mark Cave-Ayland Message-ID: <5751BA4C.7020700@ilande.co.uk> Date: Fri, 3 Jun 2016 18:11:40 +0100 MIME-Version: 1.0 In-Reply-To: <20160603154549.GA31406@ibawizard> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] Bug in ppc/BookE wait instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jakub Horak , qemu-devel@nongnu.org, "qemu-ppc@nongnu.org" , David Gibson On 03/06/16 16:45, Jakub Horak wrote: (Added David as PPC maintainer and qemu-ppc mailing list) > Hello, > I think there's a bug in "wait" instruction code generator for PowerPC > architecture. It doesn't make sense to store a non-initialized register. > > Best regards, > Jakub Horak > > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index f5ceae5..6af567b 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -3439,7 +3439,7 @@ static void gen_sync(DisasContext *ctx) > /* wait */ > static void gen_wait(DisasContext *ctx) > { > - TCGv_i32 t0 = tcg_temp_new_i32(); > + TCGv_i32 t0 = tcg_const_i32(1); > tcg_gen_st_i32(t0, cpu_env, > -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); > tcg_temp_free_i32(t0); > ATB, Mark.