From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56570) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9s4K-0002rp-3M for qemu-devel@nongnu.org; Mon, 06 Jun 2016 06:47:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b9s4F-0003Z6-UK for qemu-devel@nongnu.org; Mon, 06 Jun 2016 06:47:39 -0400 Received: from 3.mo69.mail-out.ovh.net ([188.165.52.203]:59290) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b9s4F-0003Yw-Nm for qemu-devel@nongnu.org; Mon, 06 Jun 2016 06:47:35 -0400 Received: from player798.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo69.mail-out.ovh.net (Postfix) with ESMTP id D0B44FFC52D for ; Mon, 6 Jun 2016 12:47:33 +0200 (CEST) References: <1465206768.4274.46.camel@au1.ibm.com> From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= Message-ID: <575554BF.2050702@kaod.org> Date: Mon, 6 Jun 2016 12:47:27 +0200 MIME-Version: 1.0 In-Reply-To: <1465206768.4274.46.camel@au1.ibm.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 2/2] ppc: Fix tlb invalidations on 6xx/7xx/7xxx 32-bit processors List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: benh@au1.ibm.com, qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, David Gibson , Mark Cave-Ayland On 06/06/2016 11:52 AM, Benjamin Herrenschmidt wrote: > The processor only uses some bits of the address and invalidates an > entire congruence class. Some OSes such as Darwin and HelenOS take > advantage of this and occasionally invalidate the entire TLB by just > doing a series of 64 consecutive tlbie for example. >=20 > Our code tries to be too smart here only invalidating a segment > congruence class (ie, allowing more address bits to be relevant > in the invalidation), this fails miserably on those OSes. >=20 > Instead don't bother, do like ppc64 and blow the whole tlb when tlbie > is executed. >=20 > Signed-off-by: Benjamin Herrenschmidt Looks good on G3 and G4 running macosx10.2 and macosx10.4. Tested-by: C=C3=A9dric Le Goater > --- > target-ppc/mmu_helper.c | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index f5c4e69..a5e3878 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -1969,6 +1969,11 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, ta= rget_ulong addr) > /* XXX: this case should be optimized, > * giving a mask to tlb_flush_page > */ > + /* This is broken, some CPUs invalidate a whole congruence > + * class on an even smaller subset of bits and some OSes take > + * advantage of this. Just blow the whole thing away. > + */ > +#if 0 > tlb_flush_page(cs, addr | (0x0 << 28)); > tlb_flush_page(cs, addr | (0x1 << 28)); > tlb_flush_page(cs, addr | (0x2 << 28)); > @@ -1985,6 +1990,9 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, tar= get_ulong addr) > tlb_flush_page(cs, addr | (0xD << 28)); > tlb_flush_page(cs, addr | (0xE << 28)); > tlb_flush_page(cs, addr | (0xF << 28)); > +#else > + tlb_flush(cs, 1); > +#endif > break; > #if defined(TARGET_PPC64) > case POWERPC_MMU_64B: >=20 >=20