From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yisen.zhuang@huawei.com (Yisen Zhuang) Date: Wed, 22 Jun 2016 09:33:24 +0800 Subject: [PATCH net-next 01/19] net: hns: bug fix of ge reset sequence In-Reply-To: <1466505306.30123.203.camel@linux.intel.com> References: <1466481399-70080-1-git-send-email-Yisen.Zhuang@huawei.com> <1466481399-70080-2-git-send-email-Yisen.Zhuang@huawei.com> <1466505306.30123.203.camel@linux.intel.com> Message-ID: <5769EAE4.2010507@huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org ? 2016/6/21 18:35, Andy Shevchenko ??: > On Tue, 2016-06-21 at 11:56 +0800, Yisen Zhuang wrote: >> From: Qianqian Xie >> >> The bit fileds of PPE reset register are different between HNS v1 and >> HNS v2, but the current procedure just only match HNS v1. Here is a >> patch to fix it. >> >> Signed-off-by: Kejian Yan >> Signed-off-by: Qianqian Xie >> Signed-off-by: Yisen Zhuang >> --- >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> index 96cb628..09e60d6 100644 >> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> @@ -271,7 +271,11 @@ static void hns_dsaf_ge_srst_by_port(struct >> dsaf_device *dsaf_dev, u32 port, >> } >> } else { >> reg_val_1 = 0x15540 << dsaf_dev->reset_offset; >> - reg_val_2 = 0x100 << dsaf_dev->reset_offset; >> + >> + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) >> + reg_val_2 = 0x100 << dsaf_dev->reset_offset; >> + else >> + reg_val_2 = 0x40 << dsaf_dev->reset_offset; > > reg_val_1 = 0x15540; > reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; > > reg_val_1 <<= dsaf_dev->reset_offset; > reg_val_2 <<= dsaf_dev- I will fix it with a new patch. Thanks, Yisen >> reset_offset; > > >> >> if (!dereset) { >> dsaf_write_sub(dsaf_dev, >> DSAF_SUB_SC_GE_RESET_REQ1_REG, > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751997AbcFVBhX (ORCPT ); Tue, 21 Jun 2016 21:37:23 -0400 Received: from szxga01-in.huawei.com ([58.251.152.64]:26389 "EHLO szxga01-in.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750907AbcFVBhW (ORCPT ); Tue, 21 Jun 2016 21:37:22 -0400 Subject: Re: [PATCH net-next 01/19] net: hns: bug fix of ge reset sequence To: Andy Shevchenko , , , References: <1466481399-70080-1-git-send-email-Yisen.Zhuang@huawei.com> <1466481399-70080-2-git-send-email-Yisen.Zhuang@huawei.com> <1466505306.30123.203.camel@linux.intel.com> CC: , , , , , , , , , , , From: Yisen Zhuang Message-ID: <5769EAE4.2010507@huawei.com> Date: Wed, 22 Jun 2016 09:33:24 +0800 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <1466505306.30123.203.camel@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.74.157.38] X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A090201.5769EAF1.009A,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 472c875efa83616181bec421e28441a5 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2016/6/21 18:35, Andy Shevchenko 写道: > On Tue, 2016-06-21 at 11:56 +0800, Yisen Zhuang wrote: >> From: Qianqian Xie >> >> The bit fileds of PPE reset register are different between HNS v1 and >> HNS v2, but the current procedure just only match HNS v1. Here is a >> patch to fix it. >> >> Signed-off-by: Kejian Yan >> Signed-off-by: Qianqian Xie >> Signed-off-by: Yisen Zhuang >> --- >> drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c | 6 +++++- >> 1 file changed, 5 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> index 96cb628..09e60d6 100644 >> --- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> +++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c >> @@ -271,7 +271,11 @@ static void hns_dsaf_ge_srst_by_port(struct >> dsaf_device *dsaf_dev, u32 port, >> } >> } else { >> reg_val_1 = 0x15540 << dsaf_dev->reset_offset; >> - reg_val_2 = 0x100 << dsaf_dev->reset_offset; >> + >> + if (AE_IS_VER1(dsaf_dev->dsaf_ver)) >> + reg_val_2 = 0x100 << dsaf_dev->reset_offset; >> + else >> + reg_val_2 = 0x40 << dsaf_dev->reset_offset; > > reg_val_1 = 0x15540; > reg_val_2 = AE_IS_VER1(dsaf_dev->dsaf_ver) ? 0x100 : 0x40; > > reg_val_1 <<= dsaf_dev->reset_offset; > reg_val_2 <<= dsaf_dev- I will fix it with a new patch. Thanks, Yisen >> reset_offset; > > >> >> if (!dereset) { >> dsaf_write_sub(dsaf_dev, >> DSAF_SUB_SC_GE_RESET_REQ1_REG, > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yisen Zhuang Subject: Re: [PATCH net-next 01/19] net: hns: bug fix of ge reset sequence Date: Wed, 22 Jun 2016 09:33:24 +0800 Message-ID: <5769EAE4.2010507@huawei.com> References: <1466481399-70080-1-git-send-email-Yisen.Zhuang@huawei.com> <1466481399-70080-2-git-send-email-Yisen.Zhuang@huawei.com> <1466505306.30123.203.camel@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Cc: ivecera@redhat.com, andrew@lunn.ch, liguozhu@huawei.com, arnd@arndb.de, charles.chenxin@huawei.com, linux-kernel@vger.kernel.org, linuxarm@huawei.com, geliangtang@163.com, huangdaode@hisilicon.com, netdev@vger.kernel.org, fengguang.wu@intel.com, linux-arm-kernel@lists.infradead.org To: Andy Shevchenko , , , Return-path: In-Reply-To: <1466505306.30123.203.camel@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org List-Id: netdev.vger.kernel.org CgrlnKggMjAxNi82LzIxIDE4OjM1LCBBbmR5IFNoZXZjaGVua28g5YaZ6YGTOgo+IE9uIFR1ZSwg MjAxNi0wNi0yMSBhdCAxMTo1NiArMDgwMCwgWWlzZW4gWmh1YW5nIHdyb3RlOgo+PiBGcm9tOiBR aWFucWlhbiBYaWUgPHhpZXFpYW5xaWFuQGh1YXdlaS5jb20+Cj4+Cj4+IFRoZSBiaXQgZmlsZWRz IG9mIFBQRSByZXNldCByZWdpc3RlciBhcmUgZGlmZmVyZW50IGJldHdlZW4gSE5TIHYxIGFuZAo+ PiBITlMgdjIsIGJ1dCB0aGUgY3VycmVudCBwcm9jZWR1cmUganVzdCBvbmx5IG1hdGNoIEhOUyB2 MS4gSGVyZSBpcyBhCj4+IHBhdGNoIHRvIGZpeCBpdC4KPj4KPj4gU2lnbmVkLW9mZi1ieTogS2Vq aWFuIFlhbiA8eWFua2VqaWFuQGh1YXdlaS5jb20+Cj4+IFNpZ25lZC1vZmYtYnk6IFFpYW5xaWFu IFhpZSA8eGllcWlhbnFpYW5AaHVhd2VpLmNvbT4KPj4gU2lnbmVkLW9mZi1ieTogWWlzZW4gWmh1 YW5nIDxZaXNlbi5aaHVhbmdAaHVhd2VpLmNvbT4KPj4gLS0tCj4+ICBkcml2ZXJzL25ldC9ldGhl cm5ldC9oaXNpbGljb24vaG5zL2huc19kc2FmX21pc2MuYyB8IDYgKysrKystCj4+ICAxIGZpbGUg Y2hhbmdlZCwgNSBpbnNlcnRpb25zKCspLCAxIGRlbGV0aW9uKC0pCj4+Cj4+IGRpZmYgLS1naXQg YS9kcml2ZXJzL25ldC9ldGhlcm5ldC9oaXNpbGljb24vaG5zL2huc19kc2FmX21pc2MuYwo+PiBi L2RyaXZlcnMvbmV0L2V0aGVybmV0L2hpc2lsaWNvbi9obnMvaG5zX2RzYWZfbWlzYy5jCj4+IGlu ZGV4IDk2Y2I2MjguLjA5ZTYwZDYgMTAwNjQ0Cj4+IC0tLSBhL2RyaXZlcnMvbmV0L2V0aGVybmV0 L2hpc2lsaWNvbi9obnMvaG5zX2RzYWZfbWlzYy5jCj4+ICsrKyBiL2RyaXZlcnMvbmV0L2V0aGVy bmV0L2hpc2lsaWNvbi9obnMvaG5zX2RzYWZfbWlzYy5jCj4+IEBAIC0yNzEsNyArMjcxLDExIEBA IHN0YXRpYyB2b2lkIGhuc19kc2FmX2dlX3Nyc3RfYnlfcG9ydChzdHJ1Y3QKPj4gZHNhZl9kZXZp Y2UgKmRzYWZfZGV2LCB1MzIgcG9ydCwKPj4gIAkJfQo+PiAgCX0gZWxzZSB7Cj4+ICAJCXJlZ192 YWxfMSA9IDB4MTU1NDAgPDwgZHNhZl9kZXYtPnJlc2V0X29mZnNldDsKPj4gLQkJcmVnX3ZhbF8y ID0gMHgxMDAgPDwgZHNhZl9kZXYtPnJlc2V0X29mZnNldDsKPj4gKwo+PiArCQlpZiAoQUVfSVNf VkVSMShkc2FmX2Rldi0+ZHNhZl92ZXIpKQo+PiArCQkJcmVnX3ZhbF8yID0gMHgxMDAgPDwgZHNh Zl9kZXYtPnJlc2V0X29mZnNldDsKPj4gKwkJZWxzZQo+PiArCQkJcmVnX3ZhbF8yID0gMHg0MCA8 PCBkc2FmX2Rldi0+cmVzZXRfb2Zmc2V0Owo+IAo+IHJlZ192YWxfMSA9IDB4MTU1NDA7Cj4gcmVn X3ZhbF8yID0gQUVfSVNfVkVSMShkc2FmX2Rldi0+ZHNhZl92ZXIpID8gMHgxMDAgOiAweDQwOwo+ IAo+IHJlZ192YWxfMSA8PD0gZHNhZl9kZXYtPnJlc2V0X29mZnNldDsKPiByZWdfdmFsXzIgPDw9 IGRzYWZfZGV2LQoKSSB3aWxsIGZpeCBpdCB3aXRoIGEgbmV3IHBhdGNoLgoKVGhhbmtzLAoKWWlz ZW4KCj4+IHJlc2V0X29mZnNldDsKPiAKPiAKPj4gIAo+PiAgCQlpZiAoIWRlcmVzZXQpIHsKPj4g IAkJCWRzYWZfd3JpdGVfc3ViKGRzYWZfZGV2LAo+PiBEU0FGX1NVQl9TQ19HRV9SRVNFVF9SRVEx X1JFRywKPiAKCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f XwpsaW51eC1hcm0ta2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmlu ZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9s aW51eC1hcm0ta2VybmVsCg==