From mboxrd@z Thu Jan 1 00:00:00 1970 From: Joseph Lo Subject: Re: [PATCH 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP Date: Tue, 28 Jun 2016 17:16:03 +0800 Message-ID: <57724053.6030902@nvidia.com> References: <20160627090248.23621-1-josephl@nvidia.com> <20160627090248.23621-4-josephl@nvidia.com> <57714F7D.1040301@wwwdotorg.org> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <57714F7D.1040301-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Stephen Warren Cc: Thierry Reding , Alexandre Courbot , linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, Rob Herring , Mark Rutland , Peter De Schrijver , Matthew Longnecker , devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Jassi Brar , linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Catalin Marinas , Will Deacon List-Id: linux-tegra@vger.kernel.org On 06/28/2016 12:08 AM, Stephen Warren wrote: > On 06/27/2016 03:02 AM, Joseph Lo wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management tasks >> from the CPU. The binding document defines the resources that would be >> used by the BPMP firmware driver, which can create the interprocessor >> communication (IPC) between the CPU and BPMP. > >> diff --git >> a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt >> b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt > >> +The BPMP is a specific processor in Tegra chip, which is designed for >> +booting process handling and offloading the power management tasks from >> +the CPU. The binding document defines the resources that would be >> used by >> +the BPMP firmware driver, which can create the interprocessor >> +communication (IPC) between the CPU and BPMP. > > s/power management/power management, clock management, and reset control/? Yes. > >> +Required properties: >> +- name : Should be bpmp >> +- compatible : Should be "nvidia,tegra-bpmp" > > Again, I'd suggest wording this as: > > - compatible > Array of strings. > One of: > - "nvidia,tegra186-bpmp" Okay. > >> +- mboxes : The phandle of mailbox controller and the channel ID > > s/channel ID/mailbox specifier/. > >> + See "Documentation/devicetree/bindings/mailbox/ >> + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ >> + bindings/mailbox/mailbox.txt" for more details about the generic >> + mailbox controller and mailbox client driver bindings. > > I'd rather not split the filenames across lines, since that makes grep > fail to match. Perhaps add the following text to the introductory > section at the start of the file to avoid having to mention some of the > filenames in an indented block of text: Thanks. > > ========== > This node is a mailbox consumer. See the following file for details of > the mailbox subsystem, and the specifiers implemented by the relevant > provider(s): > > - Documentation/devicetree/bindings/mailbox/mailbox.txt > - Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt > > This node is a clock and reset provider. See the following files for > general documentation of those features, and the specifiers implemented > by this node: > > - Documentation/devicetree/bindings/clock/clock-bindings.txt > - include/dt-bindings/clock/tegra186-clock.h > - Documentation/devicetree/bindings/reset/reset.txt > - include/dt-bindings/reset/tegra186-reset.h > ========== > > Related, I would expect those two header files (tegra186-clock.h and > tegra186-reset.h) to be part of this patch, since they form part of the > definition of this binding. Okay. Will add them. > >> +The shared memory bindings for BPMP >> +----------------------------------- >> + >> +The shared memory area for the IPC TX and RX between CPU and BPMP are >> +predefined and work on top of sysram, which is a sram inside the chip. > > s/a sram/an SRAM/. > >> +Example: > ... >> +bpmp@d0000000 { > > There should be no unit address ("@d0000000") in the node name, since > there's no reg property. Thanks, -Joseph -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: josephl@nvidia.com (Joseph Lo) Date: Tue, 28 Jun 2016 17:16:03 +0800 Subject: [PATCH 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP In-Reply-To: <57714F7D.1040301@wwwdotorg.org> References: <20160627090248.23621-1-josephl@nvidia.com> <20160627090248.23621-4-josephl@nvidia.com> <57714F7D.1040301@wwwdotorg.org> Message-ID: <57724053.6030902@nvidia.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/28/2016 12:08 AM, Stephen Warren wrote: > On 06/27/2016 03:02 AM, Joseph Lo wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management tasks >> from the CPU. The binding document defines the resources that would be >> used by the BPMP firmware driver, which can create the interprocessor >> communication (IPC) between the CPU and BPMP. > >> diff --git >> a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt >> b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt > >> +The BPMP is a specific processor in Tegra chip, which is designed for >> +booting process handling and offloading the power management tasks from >> +the CPU. The binding document defines the resources that would be >> used by >> +the BPMP firmware driver, which can create the interprocessor >> +communication (IPC) between the CPU and BPMP. > > s/power management/power management, clock management, and reset control/? Yes. > >> +Required properties: >> +- name : Should be bpmp >> +- compatible : Should be "nvidia,tegra-bpmp" > > Again, I'd suggest wording this as: > > - compatible > Array of strings. > One of: > - "nvidia,tegra186-bpmp" Okay. > >> +- mboxes : The phandle of mailbox controller and the channel ID > > s/channel ID/mailbox specifier/. > >> + See "Documentation/devicetree/bindings/mailbox/ >> + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ >> + bindings/mailbox/mailbox.txt" for more details about the generic >> + mailbox controller and mailbox client driver bindings. > > I'd rather not split the filenames across lines, since that makes grep > fail to match. Perhaps add the following text to the introductory > section at the start of the file to avoid having to mention some of the > filenames in an indented block of text: Thanks. > > ========== > This node is a mailbox consumer. See the following file for details of > the mailbox subsystem, and the specifiers implemented by the relevant > provider(s): > > - Documentation/devicetree/bindings/mailbox/mailbox.txt > - Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt > > This node is a clock and reset provider. See the following files for > general documentation of those features, and the specifiers implemented > by this node: > > - Documentation/devicetree/bindings/clock/clock-bindings.txt > - include/dt-bindings/clock/tegra186-clock.h > - Documentation/devicetree/bindings/reset/reset.txt > - include/dt-bindings/reset/tegra186-reset.h > ========== > > Related, I would expect those two header files (tegra186-clock.h and > tegra186-reset.h) to be part of this patch, since they form part of the > definition of this binding. Okay. Will add them. > >> +The shared memory bindings for BPMP >> +----------------------------------- >> + >> +The shared memory area for the IPC TX and RX between CPU and BPMP are >> +predefined and work on top of sysram, which is a sram inside the chip. > > s/a sram/an SRAM/. > >> +Example: > ... >> +bpmp at d0000000 { > > There should be no unit address ("@d0000000") in the node name, since > there's no reg property. Thanks, -Joseph From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752380AbcF1JQL (ORCPT ); Tue, 28 Jun 2016 05:16:11 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:25587 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752006AbcF1JQI (ORCPT ); Tue, 28 Jun 2016 05:16:08 -0400 X-PGP-Universal: processed; by hkpgpgate101.nvidia.com on Tue, 28 Jun 2016 02:16:05 -0700 Subject: Re: [PATCH 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP To: Stephen Warren References: <20160627090248.23621-1-josephl@nvidia.com> <20160627090248.23621-4-josephl@nvidia.com> <57714F7D.1040301@wwwdotorg.org> CC: Thierry Reding , Alexandre Courbot , , , Rob Herring , Mark Rutland , Peter De Schrijver , Matthew Longnecker , , Jassi Brar , , Catalin Marinas , Will Deacon From: Joseph Lo Message-ID: <57724053.6030902@nvidia.com> Date: Tue, 28 Jun 2016 17:16:03 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <57714F7D.1040301@wwwdotorg.org> X-Originating-IP: [10.19.108.111] X-ClientProxiedBy: DRBGMAIL102.nvidia.com (10.18.16.21) To HKMAIL101.nvidia.com (10.18.16.10) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/28/2016 12:08 AM, Stephen Warren wrote: > On 06/27/2016 03:02 AM, Joseph Lo wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management tasks >> from the CPU. The binding document defines the resources that would be >> used by the BPMP firmware driver, which can create the interprocessor >> communication (IPC) between the CPU and BPMP. > >> diff --git >> a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt >> b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt > >> +The BPMP is a specific processor in Tegra chip, which is designed for >> +booting process handling and offloading the power management tasks from >> +the CPU. The binding document defines the resources that would be >> used by >> +the BPMP firmware driver, which can create the interprocessor >> +communication (IPC) between the CPU and BPMP. > > s/power management/power management, clock management, and reset control/? Yes. > >> +Required properties: >> +- name : Should be bpmp >> +- compatible : Should be "nvidia,tegra-bpmp" > > Again, I'd suggest wording this as: > > - compatible > Array of strings. > One of: > - "nvidia,tegra186-bpmp" Okay. > >> +- mboxes : The phandle of mailbox controller and the channel ID > > s/channel ID/mailbox specifier/. > >> + See "Documentation/devicetree/bindings/mailbox/ >> + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ >> + bindings/mailbox/mailbox.txt" for more details about the generic >> + mailbox controller and mailbox client driver bindings. > > I'd rather not split the filenames across lines, since that makes grep > fail to match. Perhaps add the following text to the introductory > section at the start of the file to avoid having to mention some of the > filenames in an indented block of text: Thanks. > > ========== > This node is a mailbox consumer. See the following file for details of > the mailbox subsystem, and the specifiers implemented by the relevant > provider(s): > > - Documentation/devicetree/bindings/mailbox/mailbox.txt > - Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt > > This node is a clock and reset provider. See the following files for > general documentation of those features, and the specifiers implemented > by this node: > > - Documentation/devicetree/bindings/clock/clock-bindings.txt > - include/dt-bindings/clock/tegra186-clock.h > - Documentation/devicetree/bindings/reset/reset.txt > - include/dt-bindings/reset/tegra186-reset.h > ========== > > Related, I would expect those two header files (tegra186-clock.h and > tegra186-reset.h) to be part of this patch, since they form part of the > definition of this binding. Okay. Will add them. > >> +The shared memory bindings for BPMP >> +----------------------------------- >> + >> +The shared memory area for the IPC TX and RX between CPU and BPMP are >> +predefined and work on top of sysram, which is a sram inside the chip. > > s/a sram/an SRAM/. > >> +Example: > ... >> +bpmp@d0000000 { > > There should be no unit address ("@d0000000") in the node name, since > there's no reg property. Thanks, -Joseph