From mboxrd@z Thu Jan 1 00:00:00 1970 From: scott.branden@broadcom.com (Scott Branden) Date: Tue, 28 Jun 2016 15:13:59 -0700 Subject: [PATCH 1/2] arm: dts: bcm5301x: Add syscon based reboot in DT In-Reply-To: <1467151833-20767-2-git-send-email-jon.mason@broadcom.com> References: <1467151833-20767-1-git-send-email-jon.mason@broadcom.com> <1467151833-20767-2-git-send-email-jon.mason@broadcom.com> Message-ID: <5772F6A7.9080304@broadcom.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 16-06-28 03:10 PM, Jon Mason wrote: > From: Jon Mason > > Add the ability to reboot via a reset of the processor. This is > achieved via a write of 0x39 to the CRU Reset Register. Unfortunately, > this only resets the core and not the other IP blocks. So if possible, > other methods should be used on the individual boards. Is it possible to force a watchdog reset instead for reboot? > > Signed-off-by: Jon Mason > --- > arch/arm/boot/dts/bcm5301x.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index 7d4d29b..f878d0d 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -260,6 +260,18 @@ > "sata2"; > }; > > + cru: system-controller at 1800c184 { > + compatible = "brcm,bcm53010-cru", "syscon"; > + reg = <0x1800c184 0x4>; > + }; > + > + reboot at 1800c184 { > + compatible ="syscon-reboot"; > + regmap = <&cru>; > + offset = <0>; > + mask = <0x39>; > + }; > + > nand: nand at 18028000 { > compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; > reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752693AbcF1WOH (ORCPT ); Tue, 28 Jun 2016 18:14:07 -0400 Received: from mail-pf0-f170.google.com ([209.85.192.170]:34511 "EHLO mail-pf0-f170.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752395AbcF1WOE (ORCPT ); Tue, 28 Jun 2016 18:14:04 -0400 Subject: Re: [PATCH 1/2] arm: dts: bcm5301x: Add syscon based reboot in DT To: Jon Mason , Arnd Bergmann References: <1467151833-20767-1-git-send-email-jon.mason@broadcom.com> <1467151833-20767-2-git-send-email-jon.mason@broadcom.com> Cc: Florian Fainelli , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jon Mason From: Scott Branden Message-ID: <5772F6A7.9080304@broadcom.com> Date: Tue, 28 Jun 2016 15:13:59 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1467151833-20767-2-git-send-email-jon.mason@broadcom.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16-06-28 03:10 PM, Jon Mason wrote: > From: Jon Mason > > Add the ability to reboot via a reset of the processor. This is > achieved via a write of 0x39 to the CRU Reset Register. Unfortunately, > this only resets the core and not the other IP blocks. So if possible, > other methods should be used on the individual boards. Is it possible to force a watchdog reset instead for reboot? > > Signed-off-by: Jon Mason > --- > arch/arm/boot/dts/bcm5301x.dtsi | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/arch/arm/boot/dts/bcm5301x.dtsi b/arch/arm/boot/dts/bcm5301x.dtsi > index 7d4d29b..f878d0d 100644 > --- a/arch/arm/boot/dts/bcm5301x.dtsi > +++ b/arch/arm/boot/dts/bcm5301x.dtsi > @@ -260,6 +260,18 @@ > "sata2"; > }; > > + cru: system-controller@1800c184 { > + compatible = "brcm,bcm53010-cru", "syscon"; > + reg = <0x1800c184 0x4>; > + }; > + > + reboot@1800c184 { > + compatible ="syscon-reboot"; > + regmap = <&cru>; > + offset = <0>; > + mask = <0x39>; > + }; > + > nand: nand@18028000 { > compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand"; > reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>; >