From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 3/4] drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register()
Date: Thu, 30 Jun 2016 14:27:55 +0100 [thread overview]
Message-ID: <57751E5B.6050802@linux.intel.com> (raw)
In-Reply-To: <1467286215-8357-3-git-send-email-chris@chris-wilson.co.uk>
On 30/06/16 12:30, Chris Wilson wrote:
> By using the out-of-line intel_wait_for_register() not only do we can
> efficiency from using the hybrid wait_for() contained within, but we
> avoid code bloat from the numerous inlined loops:
>
> text data bss dec hex filename
> 1078551 4557 416 1083524 108884 drivers/gpu/drm/i915/i915.ko
> 1070775 4557 416 1075748 106a24 drivers/gpu/drm/i915/i915.ko
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 27 +++++++------
> drivers/gpu/drm/i915/intel_crt.c | 18 +++++----
> drivers/gpu/drm/i915/intel_ddi.c | 5 ++-
> drivers/gpu/drm/i915/intel_display.c | 69 +++++++++++++++++++++++++--------
> drivers/gpu/drm/i915/intel_dp.c | 11 ++++--
> drivers/gpu/drm/i915/intel_dp_mst.c | 7 +++-
> drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 ++-
> drivers/gpu/drm/i915/intel_dsi.c | 29 ++++++++++----
> drivers/gpu/drm/i915/intel_dsi_pll.c | 13 +++++--
> drivers/gpu/drm/i915/intel_fbc.c | 4 +-
> drivers/gpu/drm/i915/intel_i2c.c | 10 ++---
> drivers/gpu/drm/i915/intel_lrc.c | 5 ++-
> drivers/gpu/drm/i915/intel_lvds.c | 4 +-
> drivers/gpu/drm/i915/intel_psr.c | 29 +++++++++-----
> drivers/gpu/drm/i915/intel_ringbuffer.c | 19 ++++++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 47 +++++++++++++++-------
> drivers/gpu/drm/i915/intel_sideband.c | 32 ++++++++++-----
> drivers/gpu/drm/i915/intel_uncore.c | 20 +++++-----
> 18 files changed, 241 insertions(+), 114 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index b98afbd33235..c580e24095b0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2535,8 +2535,6 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
> u32 val;
> int err;
>
> -#define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
> -
> val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
> val &= ~VLV_GFX_CLK_FORCE_ON_BIT;
> if (force_on)
> @@ -2546,13 +2544,16 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
> if (!force_on)
> return 0;
>
> - err = wait_for(COND, 20);
> + err = intel_wait_for_register(dev_priv,
> + VLV_GTLC_SURVIVABILITY_REG,
> + VLV_GFX_CLK_STATUS_BIT,
> + VLV_GFX_CLK_STATUS_BIT,
> + 20);
> if (err)
> DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
> I915_READ(VLV_GTLC_SURVIVABILITY_REG));
>
> return err;
> -#undef COND
> }
>
> static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
> @@ -2567,13 +2568,15 @@ static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
> I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
> POSTING_READ(VLV_GTLC_WAKE_CTRL);
>
> -#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
> - allow)
> - err = wait_for(COND, 1);
> + err = intel_wait_for_register(dev_priv,
> + VLV_GTLC_PW_STATUS,
> + VLV_GTLC_ALLOWWAKEACK,
> + allow,
> + 1);
> if (err)
> DRM_ERROR("timeout disabling GT waking\n");
> +
> return err;
> -#undef COND
> }
>
> static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
> @@ -2585,8 +2588,7 @@ static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
>
> mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
> val = wait_for_on ? mask : 0;
> -#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
> - if (COND)
> + if ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
> return 0;
>
> DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
> @@ -2597,13 +2599,14 @@ static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
> * RC6 transitioning can be delayed up to 2 msec (see
> * valleyview_enable_rps), use 3 msec for safety.
> */
> - err = wait_for(COND, 3);
> + err = intel_wait_for_register(dev_priv,
> + VLV_GTLC_PW_STATUS, mask, val,
> + 3);
> if (err)
> DRM_ERROR("timeout waiting for GT wells to go %s\n",
> onoff(wait_for_on));
>
> return err;
> -#undef COND
> }
>
> static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
> index 165e4b901548..0c8036e1b4d7 100644
> --- a/drivers/gpu/drm/i915/intel_crt.c
> +++ b/drivers/gpu/drm/i915/intel_crt.c
> @@ -301,8 +301,10 @@ static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
>
> I915_WRITE(crt->adpa_reg, adpa);
>
> - if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
> - 1000))
> + if (intel_wait_for_register(dev_priv,
> + crt->adpa_reg,
> + ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
> + 1000))
> DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
>
> if (turn_off_dac) {
> @@ -338,8 +340,10 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>
> I915_WRITE(crt->adpa_reg, adpa);
>
> - if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
> - 1000)) {
> + if (intel_wait_for_register(dev_priv,
> + crt->adpa_reg,
> + ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 0,
> + 1000)) {
> DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
> I915_WRITE(crt->adpa_reg, save_adpa);
> }
> @@ -394,9 +398,9 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> CRT_HOTPLUG_FORCE_DETECT,
> CRT_HOTPLUG_FORCE_DETECT);
> /* wait for FORCE_DETECT to go off */
> - if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
> - CRT_HOTPLUG_FORCE_DETECT) == 0,
> - 1000))
> + if (intel_wait_for_register(dev_priv, PORT_HOTPLUG_EN,
> + CRT_HOTPLUG_FORCE_DETECT, 0,
> + 1000))
> DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index ad3b0ee5e55b..6bcd7ffbff43 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1808,7 +1808,10 @@ static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
> enum dpio_phy phy)
> {
> - if (wait_for(I915_READ(BXT_PORT_REF_DW3(phy)) & GRC_DONE, 10))
> + if (intel_wait_for_register(dev_priv,
> + BXT_PORT_REF_DW3(phy),
> + GRC_DONE, GRC_DONE,
> + 10))
> DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2acc6060b78d..30c181a72202 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1124,8 +1124,9 @@ static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
> i915_reg_t reg = PIPECONF(cpu_transcoder);
>
> /* Wait for the Pipe State to go off */
> - if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
> - 100))
> + if (intel_wait_for_register(dev_priv,
> + reg, I965_PIPECONF_ACTIVE, 0,
> + 100))
> WARN(1, "pipe_off wait timed out\n");
> } else {
> /* Wait for the display line to settle */
> @@ -1544,7 +1545,11 @@ static void _vlv_enable_pll(struct intel_crtc *crtc,
> POSTING_READ(DPLL(pipe));
> udelay(150);
>
> - if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> + if (intel_wait_for_register(dev_priv,
> + DPLL(pipe),
> + DPLL_LOCK_VLV,
> + DPLL_LOCK_VLV,
> + 1))
> DRM_ERROR("DPLL %d failed to lock\n", pipe);
> }
>
> @@ -1593,7 +1598,9 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
> I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
>
> /* Check PLL is locked */
> - if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
> + if (intel_wait_for_register(dev_priv,
> + DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
> + 1))
> DRM_ERROR("PLL %d failed to lock\n", pipe);
> }
>
> @@ -1813,7 +1820,9 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> BUG();
> }
>
> - if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
> + if (intel_wait_for_register(dev_priv,
> + dpll_reg, port_mask, expected_mask,
> + 1000))
> WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
> port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
> }
> @@ -1871,7 +1880,9 @@ static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> val |= TRANS_PROGRESSIVE;
>
> I915_WRITE(reg, val | TRANS_ENABLE);
> - if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
> + if (intel_wait_for_register(dev_priv,
> + reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
> + 100))
> DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
> }
>
> @@ -1899,7 +1910,11 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
> val |= TRANS_PROGRESSIVE;
>
> I915_WRITE(LPT_TRANSCONF, val);
> - if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
> + if (intel_wait_for_register(dev_priv,
> + LPT_TRANSCONF,
> + TRANS_STATE_ENABLE,
> + TRANS_STATE_ENABLE,
> + 100))
> DRM_ERROR("Failed to enable PCH transcoder\n");
> }
>
> @@ -1922,7 +1937,9 @@ static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
> val &= ~TRANS_ENABLE;
> I915_WRITE(reg, val);
> /* wait for PCH transcoder off, transcoder state */
> - if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
> + if (intel_wait_for_register(dev_priv,
> + reg, TRANS_STATE_ENABLE, 0,
> + 50))
> DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
>
> if (HAS_PCH_CPT(dev)) {
> @@ -1942,7 +1959,9 @@ static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
> val &= ~TRANS_ENABLE;
> I915_WRITE(LPT_TRANSCONF, val);
> /* wait for PCH transcoder off, transcoder state */
> - if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
> + if (intel_wait_for_register(dev_priv,
> + LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
> + 50))
> DRM_ERROR("Failed to disable PCH transcoder\n");
>
> /* Workaround: clear timing override bit. */
> @@ -4446,7 +4465,9 @@ void hsw_enable_ips(struct intel_crtc *crtc)
> * and don't wait for vblanks until the end of crtc_enable, then
> * the HW state readout code will complain that the expected
> * IPS_CTL value is not the one we read. */
> - if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
> + if (intel_wait_for_register(dev_priv,
> + IPS_CTL, IPS_ENABLE, IPS_ENABLE,
> + 50))
> DRM_ERROR("Timed out waiting for IPS enable\n");
> }
> }
> @@ -4465,7 +4486,9 @@ void hsw_disable_ips(struct intel_crtc *crtc)
> WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
> mutex_unlock(&dev_priv->rps.hw_lock);
> /* wait for pcode to finish disabling IPS, which may take up to 42ms */
> - if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
> + if (intel_wait_for_register(dev_priv,
> + IPS_CTL, IPS_ENABLE, 0,
> + 42))
> DRM_ERROR("Timed out waiting for IPS disable\n");
> } else {
> I915_WRITE(IPS_CTL, 0);
> @@ -5395,7 +5418,9 @@ static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
> I915_WRITE(BXT_DE_PLL_ENABLE, 0);
>
> /* Timeout 200us */
> - if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1))
> + if (intel_wait_for_register(dev_priv,
> + BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 0,
> + 1))
> DRM_ERROR("timeout waiting for DE PLL unlock\n");
>
> dev_priv->cdclk_pll.vco = 0;
> @@ -5414,7 +5439,11 @@ static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
> I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
>
> /* Timeout 200us */
> - if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1))
> + if (intel_wait_for_register(dev_priv,
> + BXT_DE_PLL_ENABLE,
> + BXT_DE_PLL_LOCK,
> + BXT_DE_PLL_LOCK,
> + 1))
> DRM_ERROR("timeout waiting for DE PLL lock\n");
>
> dev_priv->cdclk_pll.vco = vco;
> @@ -5677,7 +5706,9 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
>
> I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
>
> - if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
> + if (intel_wait_for_register(dev_priv,
> + LCPLL1_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
> + 5))
> DRM_ERROR("DPLL0 not locked\n");
>
> dev_priv->cdclk_pll.vco = vco;
> @@ -5690,7 +5721,9 @@ static void
> skl_dpll0_disable(struct drm_i915_private *dev_priv)
> {
> I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
> - if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
> + if (intel_wait_for_register(dev_priv,
> + LCPLL1_CTL, LCPLL_PLL_LOCK, 0,
> + 1))
> DRM_ERROR("Couldn't disable DPLL0\n");
>
> dev_priv->cdclk_pll.vco = 0;
> @@ -9545,7 +9578,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
> I915_WRITE(LCPLL_CTL, val);
> POSTING_READ(LCPLL_CTL);
>
> - if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
> + if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
> DRM_ERROR("LCPLL still locked\n");
>
> val = hsw_read_dcomp(dev_priv);
> @@ -9600,7 +9633,9 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
> val &= ~LCPLL_PLL_DISABLE;
> I915_WRITE(LCPLL_CTL, val);
>
> - if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
> + if (intel_wait_for_register(dev_priv,
> + LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
> + 5))
> DRM_ERROR("LCPLL not locked yet\n");
>
> if (val & LCPLL_CD_SOURCE_FCLK) {
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 6d586b72da88..0757ee427ad7 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1768,8 +1768,9 @@ static void wait_panel_status(struct intel_dp *intel_dp,
> I915_READ(pp_stat_reg),
> I915_READ(pp_ctrl_reg));
>
> - if (_wait_for((I915_READ(pp_stat_reg) & mask) == value,
> - 5 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
> + if (intel_wait_for_register(dev_priv,
> + pp_stat_reg, mask, value,
> + 5000))
> DRM_ERROR("Panel status timeout: status %08x control %08x\n",
> I915_READ(pp_stat_reg),
> I915_READ(pp_ctrl_reg));
> @@ -3321,8 +3322,10 @@ void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
> if (port == PORT_A)
> return;
>
> - if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
> - 1))
> + if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
> + DP_TP_STATUS_IDLE_DONE,
> + DP_TP_STATUS_IDLE_DONE,
> + 1))
> DRM_ERROR("Timed out waiting for DP idle patterns\n");
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dp_mst.c b/drivers/gpu/drm/i915/intel_dp_mst.c
> index 5f88e12575ac..c1d318601bf1 100644
> --- a/drivers/gpu/drm/i915/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/intel_dp_mst.c
> @@ -213,8 +213,11 @@ static void intel_mst_enable_dp(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("%d\n", intel_dp->active_mst_links);
>
> - if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_ACT_SENT),
> - 1))
> + if (intel_wait_for_register(dev_priv,
> + DP_TP_STATUS(port),
> + DP_TP_STATUS_ACT_SENT,
> + DP_TP_STATUS_ACT_SENT,
> + 1))
> DRM_ERROR("Timed out waiting for ACT sent\n");
>
> ret = drm_dp_check_act_status(&intel_dp->mst_mgr);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index e130c3ed2b6e..e19757c76db6 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -856,7 +856,11 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
> I915_WRITE(regs[pll->id].ctl,
> I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
>
> - if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(pll->id), 5))
> + if (intel_wait_for_register(dev_priv,
> + DPLL_STATUS,
> + DPLL_LOCK(pll->id),
> + DPLL_LOCK(pll->id),
> + 5))
> DRM_ERROR("DPLL %d not locked\n", pll->id);
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
> index 63b720061bd2..448741d8653b 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -90,7 +90,9 @@ static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port)
> mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY |
> LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY;
>
> - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100))
> + if (intel_wait_for_register(dev_priv,
> + MIPI_GEN_FIFO_STAT(port), mask, mask,
> + 100))
> DRM_ERROR("DPI FIFOs are not empty\n");
> }
>
> @@ -158,8 +160,10 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
>
> /* note: this is never true for reads */
> if (packet.payload_length) {
> -
> - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50))
> + if (intel_wait_for_register(dev_priv,
> + MIPI_GEN_FIFO_STAT(port),
> + data_mask, 0,
> + 50))
> DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n");
>
> write_data(dev_priv, data_reg, packet.payload,
> @@ -170,7 +174,10 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
> I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL);
> }
>
> - if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) {
> + if (intel_wait_for_register(dev_priv,
> + MIPI_GEN_FIFO_STAT(port),
> + ctrl_mask, 0,
> + 50)) {
> DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n");
> }
>
> @@ -179,7 +186,10 @@ static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host,
> /* ->rx_len is set only for reads */
> if (msg->rx_len) {
> data_mask = GEN_READ_DATA_AVAIL;
> - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50))
> + if (intel_wait_for_register(dev_priv,
> + MIPI_INTR_STAT(port),
> + data_mask, data_mask,
> + 50))
> DRM_ERROR("Timeout waiting for read data.\n");
>
> read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len);
> @@ -269,7 +279,9 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
> I915_WRITE(MIPI_DPI_CONTROL(port), cmd);
>
> mask = SPL_PKT_SENT_INTERRUPT;
> - if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100))
> + if (intel_wait_for_register(dev_priv,
> + MIPI_INTR_STAT(port), mask, mask,
> + 100))
> DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd);
>
> return 0;
> @@ -667,8 +679,9 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
> /* Wait till Clock lanes are in LP-00 state for MIPI Port A
> * only. MIPI Port C has no similar bit for checking
> */
> - if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT)
> - == 0x00000), 30))
> + if (intel_wait_for_register(dev_priv,
> + port_ctrl, AFE_LATCHOUT, 0,
> + 30))
> DRM_ERROR("DSI LP not going Low\n");
>
> /* Disable MIPI PHY transparent latch */
> diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c
> index 1765e6e18f2c..4f9930bc89e5 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
> @@ -234,8 +234,11 @@ static void bxt_disable_dsi_pll(struct intel_encoder *encoder)
> * PLL lock should deassert within 200us.
> * Wait up to 1ms before timing out.
> */
> - if (wait_for((I915_READ(BXT_DSI_PLL_ENABLE)
> - & BXT_DSI_PLL_LOCKED) == 0, 1))
> + if (intel_wait_for_register(dev_priv,
> + BXT_DSI_PLL_ENABLE,
> + BXT_DSI_PLL_LOCKED,
> + 0,
> + 1))
> DRM_ERROR("Timeout waiting for PLL lock deassertion\n");
> }
>
> @@ -486,7 +489,11 @@ static void bxt_enable_dsi_pll(struct intel_encoder *encoder,
> I915_WRITE(BXT_DSI_PLL_ENABLE, val);
>
> /* Timeout and fail if PLL not locked */
> - if (wait_for(I915_READ(BXT_DSI_PLL_ENABLE) & BXT_DSI_PLL_LOCKED, 1)) {
> + if (intel_wait_for_register(dev_priv,
> + BXT_DSI_PLL_ENABLE,
> + BXT_DSI_PLL_LOCKED,
> + BXT_DSI_PLL_LOCKED,
> + 1)) {
> DRM_ERROR("Timed out waiting for DSI PLL to lock\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 97110533dcaa..978d79532f96 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -124,7 +124,9 @@ static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
> I915_WRITE(FBC_CONTROL, fbc_ctl);
>
> /* Wait for compressing bit to clear */
> - if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
> + if (intel_wait_for_register(dev_priv,
> + FBC_STATUS, FBC_STAT_COMPRESSING, 0,
> + 10)) {
> DRM_DEBUG_KMS("FBC idle timed out\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 81de23098be7..6bc4c064df0b 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -298,15 +298,16 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
> {
> int ret;
>
> -#define C ((I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0)
> -
> if (!HAS_GMBUS_IRQ(dev_priv))
> - return wait_for(C, 10);
> + return intel_wait_for_register(dev_priv,
> + GMBUS2, GMBUS_ACTIVE, 0,
> + 10);
>
> /* Important: The hw handles only the first bit, so set only one! */
> I915_WRITE(GMBUS4, GMBUS_IDLE_EN);
>
> - ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
> + ret = wait_event_timeout(dev_priv->gmbus_wait_queue,
> + (I915_READ_NOTRACE(GMBUS2) & GMBUS_ACTIVE) == 0,
> msecs_to_jiffies_timeout(10));
>
> I915_WRITE(GMBUS4, 0);
> @@ -315,7 +316,6 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
> return 0;
> else
> return -ETIMEDOUT;
> -#undef C
> }
>
> static int
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 62b0dc6c2642..339d8041075f 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -929,7 +929,10 @@ void intel_logical_ring_stop(struct intel_engine_cs *engine)
>
> /* TODO: Is this correct with Execlists enabled? */
> I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
> - if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
> + if (intel_wait_for_register(dev_priv,
> + RING_MI_MODE(engine->mmio_base),
> + MODE_IDLE, MODE_IDLE,
> + 1000)) {
> DRM_ERROR("%s :timed out trying to stop ring\n", engine->name);
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
> index cf680661454b..c26ffef80692 100644
> --- a/drivers/gpu/drm/i915/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/intel_lvds.c
> @@ -231,7 +231,7 @@ static void intel_enable_lvds(struct intel_encoder *encoder)
>
> I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
> POSTING_READ(lvds_encoder->reg);
> - if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
> + if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, PP_ON, 1000))
> DRM_ERROR("timed out waiting for panel to power on\n");
>
> intel_panel_enable_backlight(intel_connector);
> @@ -253,7 +253,7 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
> }
>
> I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
> - if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
> + if (intel_wait_for_register(dev_priv, stat_reg, PP_ON, 0, 1000))
> DRM_ERROR("timed out waiting for panel to power off\n");
>
> I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 29a09bf6bd18..8d25c45aa6fe 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -501,8 +501,11 @@ static void vlv_psr_disable(struct intel_dp *intel_dp)
>
> if (dev_priv->psr.active) {
> /* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
> - if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
> - VLV_EDP_PSR_IN_TRANS) == 0, 1))
> + if (intel_wait_for_register(dev_priv,
> + VLV_PSRSTAT(intel_crtc->pipe),
> + VLV_EDP_PSR_IN_TRANS,
> + 0,
> + 1))
> WARN(1, "PSR transition took longer than expected\n");
>
> val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
> @@ -528,9 +531,11 @@ static void hsw_psr_disable(struct intel_dp *intel_dp)
> I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE);
>
> /* Wait till PSR is idle */
> - if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
> - EDP_PSR_STATUS_STATE_MASK) == 0,
> - 2 * USEC_PER_SEC, 10 * USEC_PER_MSEC))
> + if (intel_wait_for_register(dev_priv,
> + EDP_PSR_STATUS_CTL,
> + EDP_PSR_STATUS_STATE_MASK,
> + 0,
> + 2000))
> DRM_ERROR("Timed out waiting for PSR Idle State\n");
>
> dev_priv->psr.active = false;
> @@ -586,14 +591,20 @@ static void intel_psr_work(struct work_struct *work)
> * and be ready for re-enable.
> */
> if (HAS_DDI(dev_priv)) {
> - if (wait_for((I915_READ(EDP_PSR_STATUS_CTL) &
> - EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
> + if (intel_wait_for_register(dev_priv,
> + EDP_PSR_STATUS_CTL,
> + EDP_PSR_STATUS_STATE_MASK,
> + 0,
> + 50)) {
> DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> return;
> }
> } else {
> - if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
> - VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
> + if (intel_wait_for_register(dev_priv,
> + VLV_PSRSTAT(pipe),
> + VLV_EDP_PSR_IN_TRANS,
> + 0,
> + 1)) {
> DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 04a2d141e690..c4365cc1f133 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -515,8 +515,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
> I915_WRITE(reg,
> _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> INSTPM_SYNC_FLUSH));
> - if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0,
> - 1000))
> + if (intel_wait_for_register(dev_priv,
> + reg, INSTPM_SYNC_FLUSH, 0,
> + 1000))
> DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
> engine->name);
> }
> @@ -528,7 +529,11 @@ static bool stop_ring(struct intel_engine_cs *engine)
>
> if (!IS_GEN2(dev_priv)) {
> I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
> - if (wait_for((I915_READ_MODE(engine) & MODE_IDLE) != 0, 1000)) {
> + if (intel_wait_for_register(dev_priv,
> + RING_MI_MODE(engine->mmio_base),
> + MODE_IDLE,
> + MODE_IDLE,
> + 1000)) {
> DRM_ERROR("%s : timed out trying to stop ring\n",
> engine->name);
> /* Sometimes we observe that the idle flag is not
> @@ -2691,9 +2696,11 @@ static void gen6_bsd_ring_write_tail(struct intel_engine_cs *engine,
> I915_WRITE64(GEN6_BSD_RNCID, 0x0);
>
> /* Wait for the ring not to be idle, i.e. for it to wake up. */
> - if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
> - GEN6_BSD_SLEEP_INDICATOR) == 0,
> - 50))
> + if (intel_wait_for_register(dev_priv,
> + GEN6_BSD_SLEEP_PSMI_CONTROL,
> + GEN6_BSD_SLEEP_INDICATOR,
> + 0,
> + 50))
> DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
>
> /* Now that the ring is fully powered up, update the tail */
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 22b46f5f0273..7cbba42f0ab4 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -365,8 +365,11 @@ static void hsw_set_power_well(struct drm_i915_private *dev_priv,
>
> if (!is_enabled) {
> DRM_DEBUG_KMS("Enabling power well\n");
> - if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
> - HSW_PWR_WELL_STATE_ENABLED), 20))
> + if (intel_wait_for_register(dev_priv,
> + HSW_PWR_WELL_DRIVER,
> + HSW_PWR_WELL_STATE_ENABLED,
> + HSW_PWR_WELL_STATE_ENABLED,
> + 20))
> DRM_ERROR("Timeout enabling power well\n");
> hsw_power_well_post_enable(dev_priv);
> }
> @@ -700,8 +703,11 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>
> switch (power_well->data) {
> case SKL_DISP_PW_1:
> - if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> - SKL_FUSE_PG0_DIST_STATUS), 1)) {
> + if (intel_wait_for_register(dev_priv,
> + SKL_FUSE_STATUS,
> + SKL_FUSE_PG0_DIST_STATUS,
> + SKL_FUSE_PG0_DIST_STATUS,
> + 1)) {
> DRM_ERROR("PG0 not enabled\n");
> return;
> }
> @@ -762,12 +768,18 @@ static void skl_set_power_well(struct drm_i915_private *dev_priv,
>
> if (check_fuse_status) {
> if (power_well->data == SKL_DISP_PW_1) {
> - if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> - SKL_FUSE_PG1_DIST_STATUS), 1))
> + if (intel_wait_for_register(dev_priv,
> + SKL_FUSE_STATUS,
> + SKL_FUSE_PG1_DIST_STATUS,
> + SKL_FUSE_PG1_DIST_STATUS,
> + 1))
> DRM_ERROR("PG1 distributing status timeout\n");
> } else if (power_well->data == SKL_DISP_PW_2) {
> - if (wait_for((I915_READ(SKL_FUSE_STATUS) &
> - SKL_FUSE_PG2_DIST_STATUS), 1))
> + if (intel_wait_for_register(dev_priv,
> + SKL_FUSE_STATUS,
> + SKL_FUSE_PG2_DIST_STATUS,
> + SKL_FUSE_PG2_DIST_STATUS,
> + 1))
> DRM_ERROR("PG2 distributing status timeout\n");
> }
> }
> @@ -1206,7 +1218,6 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> u32 phy_control = dev_priv->chv_phy_control;
> u32 phy_status = 0;
> u32 phy_status_mask = 0xffffffff;
> - u32 tmp;
>
> /*
> * The BIOS can leave the PHY is some weird state
> @@ -1294,10 +1305,14 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> * The PHY may be busy with some initial calibration and whatnot,
> * so the power state can take a while to actually change.
> */
> - if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
> - WARN(phy_status != tmp,
> - "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
> - tmp, phy_status, dev_priv->chv_phy_control);
> + if (intel_wait_for_register(dev_priv,
> + DISPLAY_PHY_STATUS,
> + phy_status_mask,
> + phy_status,
> + 10))
> + DRM_ERROR("Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
> + I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,
> + phy_status, dev_priv->chv_phy_control);
> }
>
> #undef BITS_SET
> @@ -1325,7 +1340,11 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> vlv_set_power_well(dev_priv, power_well, true);
>
> /* Poll for phypwrgood signal */
> - if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
> + if (intel_wait_for_register(dev_priv,
> + DISPLAY_PHY_STATUS,
> + PHY_POWERGOOD(phy),
> + PHY_POWERGOOD(phy),
> + 1))
> DRM_ERROR("Display PHY %d is not power up\n", phy);
>
> mutex_lock(&dev_priv->sb_lock);
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index c3998188cf35..1a840bf92eea 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -51,7 +51,9 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
>
> WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
>
> - if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
> + if (intel_wait_for_register(dev_priv,
> + VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
> + 5)) {
> DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
> is_read ? "read" : "write");
> return -EAGAIN;
> @@ -62,7 +64,9 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
> I915_WRITE(VLV_IOSF_DATA, *val);
> I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
>
> - if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
> + if (intel_wait_for_register(dev_priv,
> + VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
> + 5)) {
> DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
> is_read ? "read" : "write");
> return -ETIMEDOUT;
> @@ -202,8 +206,9 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> u32 value = 0;
> WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
>
> - if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
> - 100)) {
> + if (intel_wait_for_register(dev_priv,
> + SBI_CTL_STAT, SBI_BUSY, 0,
> + 100)) {
> DRM_ERROR("timeout waiting for SBI to become ready\n");
> return 0;
> }
> @@ -216,8 +221,11 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
> I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
>
> - if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
> - 100)) {
> + if (intel_wait_for_register(dev_priv,
> + SBI_CTL_STAT,
> + SBI_BUSY | SBI_RESPONSE_FAIL,
> + 0,
> + 100)) {
> DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
> return 0;
> }
> @@ -232,8 +240,9 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
>
> WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
>
> - if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
> - 100)) {
> + if (intel_wait_for_register(dev_priv,
> + SBI_CTL_STAT, SBI_BUSY, 0,
> + 100)) {
> DRM_ERROR("timeout waiting for SBI to become ready\n");
> return;
> }
> @@ -247,8 +256,11 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
> I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
>
> - if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
> - 100)) {
> + if (intel_wait_for_register(dev_priv,
> + SBI_CTL_STAT,
> + SBI_BUSY | SBI_RESPONSE_FAIL,
> + 0,
> + 100)) {
> DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
> return;
> }
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 4c166f6550be..b49a95a18da4 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -1530,15 +1530,17 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
>
> I915_WRITE(ILK_GDSR,
> ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
> - ret = wait_for((I915_READ(ILK_GDSR) &
> - ILK_GRDOM_RESET_ENABLE) == 0, 500);
> + ret = intel_wait_for_register(dev_priv,
> + ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
> + 500);
> if (ret)
> return ret;
>
> I915_WRITE(ILK_GDSR,
> ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
> - ret = wait_for((I915_READ(ILK_GDSR) &
> - ILK_GRDOM_RESET_ENABLE) == 0, 500);
> + ret = intel_wait_for_register(dev_priv,
> + ILK_GDSR, ILK_GRDOM_RESET_ENABLE, 0,
> + 500);
> if (ret)
> return ret;
>
> @@ -1551,20 +1553,16 @@ static int ironlake_do_reset(struct drm_i915_private *dev_priv,
> static int gen6_hw_domain_reset(struct drm_i915_private *dev_priv,
> u32 hw_domain_mask)
> {
> - int ret;
> -
> /* GEN6_GDRST is not in the gt power well, no need to check
> * for fifo space for the write or forcewake the chip for
> * the read
> */
> __raw_i915_write32(dev_priv, GEN6_GDRST, hw_domain_mask);
>
> -#define ACKED ((__raw_i915_read32(dev_priv, GEN6_GDRST) & hw_domain_mask) == 0)
> /* Spin waiting for the device to ack the reset requests */
> - ret = wait_for(ACKED, 500);
> -#undef ACKED
> -
> - return ret;
> + return intel_wait_for_register_fw(dev_priv,
> + GEN6_GDRST, hw_domain_mask, 0,
> + 500);
> }
>
> /**
>
Read it all and did not spot any errors.
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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next prev parent reply other threads:[~2016-06-30 13:27 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-30 11:30 [PATCH 1/4] drm/i915: Use a hybrid scheme for fast register waits Chris Wilson
2016-06-30 11:30 ` [PATCH 2/4] drm/i915: Convert sandybridge_pcode_*() to use intel_wait_for_register() Chris Wilson
2016-06-30 13:04 ` Tvrtko Ursulin
2016-06-30 13:19 ` Chris Wilson
2016-06-30 13:39 ` Tvrtko Ursulin
2016-06-30 19:21 ` Matt Turner
2016-06-30 11:30 ` [PATCH 3/4] drm/i915: Convert wait_for(I915_READ(reg)) to intel_wait_for_register() Chris Wilson
2016-06-30 13:27 ` Tvrtko Ursulin [this message]
2016-06-30 13:34 ` Chris Wilson
2016-06-30 13:42 ` Tvrtko Ursulin
2016-06-30 11:30 ` [PATCH 4/4] drm/i915: Perform Sandybridge BSD tail write under the forcewake Chris Wilson
2016-06-30 13:32 ` Tvrtko Ursulin
2016-06-30 12:05 ` ✗ Ro.CI.BAT: warning for series starting with [1/4] drm/i915: Use a hybrid scheme for fast register waits Patchwork
2016-06-30 12:58 ` [PATCH 1/4] " Tvrtko Ursulin
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