From: Arun Siluvery <arun.siluvery@linux.intel.com>
To: "Song, Ruiling" <ruiling.song@intel.com>,
"Yang, Rong R" <rong.r.yang@intel.com>,
"beignet@lists.freedesktop.org" <beignet@lists.freedesktop.org>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] Runtime: set the sub slice according to kernel pooled EU configure.
Date: Fri, 1 Jul 2016 14:44:40 +0100 [thread overview]
Message-ID: <577673C8.30303@linux.intel.com> (raw)
In-Reply-To: <148B1B7A67D1C24B9EF0BE42EA4977064E4C1686@shsmsx102.ccr.corp.intel.com>
On 30/06/2016 09:43, Song, Ruiling wrote:
> LGTM
>
> Ruiling
Could you please let me know whether these patches are merged/yet to be
merged?
I have submitted kernel patch which is ready to be merged but we would
like to know if userspace bits are merged or not?
https://lists.freedesktop.org/archives/intel-gfx/2016-July/099822.html
regards
Arun
>
>> -----Original Message-----
>> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of
>> Yang Rong
>> Sent: Wednesday, June 15, 2016 4:20 PM
>> To: beignet@lists.freedesktop.org; intel-gfx@lists.freedesktop.org;
>> arun.siluvery@linux.intel.com
>> Subject: [Intel-gfx] [PATCH] Runtime: set the sub slice according to kernel
>> pooled EU configure.
>>
>> If BXT pooled EU enable, the 3*6 EUs is split into 2 pooled, so change
>> the sub slice to 2.
>> For min no. of eu in pool, only affact fused down 2*6 BXT devices,
>> because beignet don't support these devices now, add assert only.
>> assert.
>>
>> This patch is based on kernel patch:
>> https://patchwork.freedesktop.org/series/8200/
>> Thanks Arun.
>>
>> Signed-off-by: Yang Rong <rong.r.yang@intel.com>
>> ---
>> CMakeLists.txt | 12 ++++++++++++
>> src/CMakeLists.txt | 10 ++++++++++
>> src/intel/intel_driver.c | 15 +++++++++++++++
>> 3 files changed, 37 insertions(+)
>>
>> diff --git a/CMakeLists.txt b/CMakeLists.txt
>> index fae3e88..af684ed 100644
>> --- a/CMakeLists.txt
>> +++ b/CMakeLists.txt
>> @@ -153,6 +153,18 @@ IF(DRM_INTEL_FOUND)
>> ELSE(HAVE_DRM_INTEL_SUBSLICE_TOTAL)
>> MESSAGE(STATUS "Disable subslice total query support")
>> ENDIF(HAVE_DRM_INTEL_SUBSLICE_TOTAL)
>> + CHECK_LIBRARY_EXISTS(drm_intel "drm_intel_get_pooled_eu" ""
>> HAVE_DRM_INTEL_POOLED_EU)
>> + IF(HAVE_DRM_INTEL_POOLED_EU)
>> + MESSAGE(STATUS "Enable pooled eu query support")
>> + ELSE(HAVE_DRM_INTEL_POOLED_EU)
>> + MESSAGE(STATUS "Disable pooled eu query support")
>> + ENDIF(HAVE_DRM_INTEL_POOLED_EU)
>> + CHECK_LIBRARY_EXISTS(drm_intel "drm_intel_get_min_eu_in_pool" ""
>> HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> + IF(HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> + MESSAGE(STATUS "Enable min eu in pool query support")
>> + ELSE(HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> + MESSAGE(STATUS "Disable min eu in pool query support")
>> + ENDIF(HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> ELSE(DRM_INTEL_FOUND)
>> MESSAGE(FATAL_ERROR "Looking for DRM Intel (>= 2.4.52) - not found")
>> ENDIF(DRM_INTEL_FOUND)
>> diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt
>> index 98f8423..a002865 100644
>> --- a/src/CMakeLists.txt
>> +++ b/src/CMakeLists.txt
>> @@ -138,6 +138,16 @@ if (HAVE_DRM_INTEL_SUBSLICE_TOTAL)
>> SET(CMAKE_C_FLAGS "-DHAS_SUBSLICE_TOTAL ${CMAKE_C_FLAGS}")
>> endif (HAVE_DRM_INTEL_SUBSLICE_TOTAL)
>>
>> +if (HAVE_DRM_INTEL_POOLED_EU)
>> + SET(CMAKE_CXX_FLAGS "-DHAS_POOLED_EU ${CMAKE_CXX_FLAGS}")
>> + SET(CMAKE_C_FLAGS "-DHAS_POOLED_EU ${CMAKE_C_FLAGS}")
>> +endif (HAVE_DRM_INTEL_POOLED_EU)
>> +
>> +if (HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> + SET(CMAKE_CXX_FLAGS "-DHAS_MIN_EU_IN_POOL ${CMAKE_CXX_FLAGS}")
>> + SET(CMAKE_C_FLAGS "-DHAS_MIN_EU_IN_POOL ${CMAKE_C_FLAGS}")
>> +endif (HAVE_DRM_INTEL_MIN_EU_IN_POOL)
>> +
>> set(GIT_SHA1 "git_sha1.h")
>> add_custom_target(${GIT_SHA1} ALL
>> COMMAND chmod +x ${CMAKE_CURRENT_SOURCE_DIR}/git_sha1.sh
>> diff --git a/src/intel/intel_driver.c b/src/intel/intel_driver.c
>> index 03d9d34..8f2373b 100644
>> --- a/src/intel/intel_driver.c
>> +++ b/src/intel/intel_driver.c
>> @@ -882,6 +882,21 @@ intel_update_device_info(cl_device_id device)
>> #endif
>> }
>> #endif
>> +
>> +#ifdef HAS_POOLED_EU
>> + /* BXT pooled eu, 3*6 to 2*9, like sub slice count is 2 */
>> + unsigned int has_pooled_eu = 0;
>> + if(!drm_intel_get_pooled_eu(driver->fd, &has_pooled_eu) && has_pooled_eu)
>> + device->sub_slice_count = 2;
>> +
>> +#ifdef HAS_MIN_EU_IN_POOL
>> + unsigned int min_eu;
>> + /* for fused down 2x6 devices, beignet don't support. */
>> + if (has_pooled_eu && !drm_intel_get_min_eu_in_pool(driver->fd, &min_eu)) {
>> + assert(min_eu == 9); //don't support fuse down device.
>> + }
>> +#endif //HAS_MIN_EU_IN_POOL
>> +#endif //HAS_POOLED_EU
>> //We should get the device memory dynamically, but the
>> //mapablce mem size usage is unknown. Just ignore it.
>> size_t total_mem,map_mem;
>> --
>> 2.1.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
prev parent reply other threads:[~2016-07-01 13:44 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-15 8:19 [PATCH] Runtime: set the sub slice according to kernel pooled EU configure Yang Rong
2016-06-15 8:19 ` [PATCH] intel: Export pooled EU and min no. of eus in a pool Yang Rong
2016-06-15 8:17 ` Arun Siluvery
2016-06-30 8:58 ` Yang, Rong R
2016-06-30 10:30 ` [Beignet] " Arun Siluvery
2016-07-05 10:01 ` Arun Siluvery
2016-07-06 3:00 ` Yang, Rong R
2016-06-23 8:52 ` ✗ Ro.CI.BAT: failure for Runtime: set the sub slice according to kernel pooled EU configure Patchwork
2016-06-30 8:43 ` [PATCH] " Song, Ruiling
2016-07-01 13:44 ` Arun Siluvery [this message]
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