diff for duplicates of <57771A39.8060606@rock-chips.com>

diff --git a/a/1.txt b/N1/1.txt
index f5c0333..e0c12d0 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,5 +1,5 @@
 
-On 2016年07月02日 00:56, Doug Anderson wrote:
+On 2016?07?02? 00:56, Doug Anderson wrote:
 > Caesar
 >
 > On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang <wxt@rock-chips.com> wrote:
@@ -44,9 +44,9 @@ At least, the gmac had been supported in rockchip inside.
 That's seem the gmac driver can't handle the power domain enough.
 --
 
-Frankly, I'm no test the GMAC，then this patch should support most of 
+Frankly, I'm no test the GMAC?then this patch should support most of 
 devices.
-We can send another patch to support it if someone（usb/gmac) can handle 
+We can send another patch to support it if someone?usb/gmac) can handle 
 the power domain.
 
 >
@@ -55,12 +55,12 @@ the power domain.
 >
 >
 
-willam@RK, what's think of it？
+willam at RK, what's think of it?
 
 >> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 >> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
->> Cc: linux-arm-kernel@lists.infradead.org
->> Cc: linux-rockchip@lists.infradead.org
+>> Cc: linux-arm-kernel at lists.infradead.org
+>> Cc: linux-rockchip at lists.infradead.org
 >> Cc: Heiko Stuebner <heiko@sntech.de>
 >>
 >> ---
@@ -83,82 +83,82 @@ willam@RK, what's think of it？
 >>                  status = "disabled";
 >>          };
 >>
->> +       qos_hdcp: qos_hdcp@ffa90000 {
+>> +       qos_hdcp: qos_hdcp at ffa90000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffa90000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_iep: qos_iep@ffa98000 {
+>> +       qos_iep: qos_iep at ffa98000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffa98000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_isp0_m0: qos_isp0_m0@ffaa0000 {
+>> +       qos_isp0_m0: qos_isp0_m0 at ffaa0000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffaa0000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_isp0_m1: qos_isp0_m1@ffaa0080 {
+>> +       qos_isp0_m1: qos_isp0_m1 at ffaa0080 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffaa0080 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_isp1_m0: qos_isp1_m0@ffaa8000 {
+>> +       qos_isp1_m0: qos_isp1_m0 at ffaa8000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffaa8000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_isp1_m1: qos_isp1_m1@ffaa8080 {
+>> +       qos_isp1_m1: qos_isp1_m1 at ffaa8080 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffaa8080 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_rga_r: qos_rga_r@ffab0000 {
+>> +       qos_rga_r: qos_rga_r at ffab0000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffab0000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_rga_w: qos_rga_w@ffab0080 {
+>> +       qos_rga_w: qos_rga_w at ffab0080 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffab0080 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_video_m0: qos_video_m0@ffab8000 {
+>> +       qos_video_m0: qos_video_m0 at ffab8000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffab8000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_video_m1_r: qos_video_m1_r@ffac0000 {
+>> +       qos_video_m1_r: qos_video_m1_r at ffac0000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffac0000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_video_m1_w: qos_video_m1_w@ffac0080 {
+>> +       qos_video_m1_w: qos_video_m1_w at ffac0080 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffac0080 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_vop_big_r: qos_vop_big_r@ffac8000 {
+>> +       qos_vop_big_r: qos_vop_big_r at ffac8000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffac8000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_vop_big_w: qos_vop_big_w@ffac8080 {
+>> +       qos_vop_big_w: qos_vop_big_w at ffac8080 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffac8080 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_vop_little: qos_vop_little@ffad0000 {
+>> +       qos_vop_little: qos_vop_little at ffad0000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffad0000 0x0 0x20>;
 >> +       };
 >> +
->> +       qos_gpu: qos_gpu@ffae0000 {
+>> +       qos_gpu: qos_gpu at ffae0000 {
 >> +               compatible = "syscon";
 >> +               reg = <0x0 0xffae0000 0x0 0x20>;
 >> +       };
 >> +
->> +       pmu: power-management@ff310000 {
+>> +       pmu: power-management at ff310000 {
 >> +               compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 >> +               reg = <0x0 0xff310000 0x0 0x1000>;
 >> +
@@ -177,45 +177,45 @@ willam@RK, what's think of it？
 >> +                       #size-cells = <0>;
 >> +
 >> +                       /* These power domains are grouped by VD_LOGIC */
->> +                       pd_vio@RK3399_PD_VIO {
+>> +                       pd_vio at RK3399_PD_VIO {
 >> +                               reg = <RK3399_PD_VIO>;
 >> +                               #address-cells = <1>;
 >> +                               #size-cells = <0>;
 >> +
->> +                               pd_isp0@RK3399_PD_ISP0 {
+>> +                               pd_isp0 at RK3399_PD_ISP0 {
 >> +                                       reg = <RK3399_PD_ISP0>;
 >> +                                       clocks = <&cru ACLK_ISP0>,
 >> +                                                <&cru HCLK_ISP0>;
 >> +                                       pm_qos = <&qos_isp0_m0>,
 >> +                                                <&qos_isp0_m1>;
 >> +                               };
->> +                               pd_isp1@RK3399_PD_ISP1 {
+>> +                               pd_isp1 at RK3399_PD_ISP1 {
 >> +                                       reg = <RK3399_PD_ISP1>;
 >> +                                       clocks = <&cru ACLK_ISP1>,
 >> +                                                <&cru HCLK_ISP1>;
 >> +                                       pm_qos = <&qos_isp1_m0>,
 >> +                                                <&qos_isp1_m1>;
 >> +                               };
->> +                               pd_vo@RK3399_PD_VO {
+>> +                               pd_vo at RK3399_PD_VO {
 >> +                                       reg = <RK3399_PD_VO>;
 >> +                                       #address-cells = <1>;
 >> +                                       #size-cells = <0>;
 >> +
->> +                                       pd_vopb@RK3399_PD_VOPB {
+>> +                                       pd_vopb at RK3399_PD_VOPB {
 >> +                                               reg = <RK3399_PD_VOPB>;
 >> +                                               clocks = <&cru ACLK_VOP0>,
 >> +                                                        <&cru HCLK_VOP0>;
 >> +                                               pm_qos = <&qos_vop_big_r>,
 >> +                                                        <&qos_vop_big_w>;
 >> +                                       };
->> +                                       pd_vopl@RK3399_PD_VOP {
+>> +                                       pd_vopl at RK3399_PD_VOP {
 >> +                                               reg = <RK3399_PD_VOPL>;
 >> +                                               clocks = <&cru ACLK_VOP1>,
 >> +                                                        <&cru HCLK_VOP1>;
 >> +                                               pm_qos = <&qos_vop_little>;
 >> +                                       };
 >> +                               };
->> +                               pd_hdcp@RK3399_PD_HDCP {
+>> +                               pd_hdcp at RK3399_PD_HDCP {
 >> +                                       reg = <RK3399_PD_HDCP>;
 >> +                                       clocks = <&cru ACLK_HDCP>,
 >> +                                                <&cru HCLK_HDCP>,
@@ -232,27 +232,27 @@ domain.
 >> +                       };
 >> +
 >> +                       /* These power domains are grouped by VD_CENTER */
->> +                       pd_vcodec@RK3399_PD_VCODEC {
+>> +                       pd_vcodec at RK3399_PD_VCODEC {
 >> +                               reg = <RK3399_PD_VCODEC>;
 >> +                               clocks = <&cru ACLK_VCODEC>,
 >> +                                        <&cru HCLK_VCODEC>;
 >> +                               pm_qos = <&qos_video_m0>;
 >> +                       };
->> +                       pd_vdu@RK3399_PD_VDU {
+>> +                       pd_vdu at RK3399_PD_VDU {
 >> +                               reg = <RK3399_PD_VDU>;
 >> +                               clocks = <&cru ACLK_VDU>,
 >> +                                        <&cru HCLK_VDU>;
 >> +                               pm_qos = <&qos_video_m1_r>,
 >> +                                        <&qos_video_m1_w>;
 >> +                       };
->> +                       pd_rga@RK3399_PD_RGA {
+>> +                       pd_rga at RK3399_PD_RGA {
 >> +                               reg = <RK3399_PD_RGA>;
 >> +                               clocks = <&cru ACLK_RGA>,
 >> +                                        <&cru HCLK_RGA>;
 >> +                               pm_qos = <&qos_rga_r>,
 >> +                                        <&qos_rga_w>;
 >> +                       };
->> +                       pd_iep@RK3399_PD_IE {
+>> +                       pd_iep at RK3399_PD_IE {
 >> +                               reg = <RK3399_PD_IEP>;
 >> +                               clocks = <&cru ACLK_IEP>,
 >> +                                        <&cru HCLK_IEP>;
@@ -264,7 +264,7 @@ Ditto
 >
 >> +
 >> +                       /* These power domains are grouped by VD_GPU */
->> +                       pd_gpu@RK3399_PD_GPU {
+>> +                       pd_gpu at RK3399_PD_GPU {
 >> +                               reg = <RK3399_PD_GPU>;
 >> +                               clocks = <&cru ACLK_GPU>;
 >> +                               pm_qos = <&qos_gpu>;
@@ -272,7 +272,7 @@ Ditto
 >> +               };
 >> +       };
 >> +
->>          pmugrf: syscon@ff320000 {
+>>          pmugrf: syscon at ff320000 {
 >>                  compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 >>                  reg = <0x0 0xff320000 0x0 0x1000>;
 >> --
@@ -280,16 +280,9 @@ Ditto
 >>
 > _______________________________________________
 > Linux-rockchip mailing list
-> Linux-rockchip@lists.infradead.org
+> Linux-rockchip at lists.infradead.org
 > http://lists.infradead.org/mailman/listinfo/linux-rockchip
 
 
 -- 
-caesar wang | software engineer | wxt@rock-chip.com
-
-
-
-_______________________________________________
-Linux-rockchip mailing list
-Linux-rockchip@lists.infradead.org
-http://lists.infradead.org/mailman/listinfo/linux-rockchip
+caesar wang | software engineer | wxt at rock-chip.com
diff --git a/a/content_digest b/N1/content_digest
index 1563c8d..637ff39 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,23 +1,13 @@
  "ref\01467347575-11806-1-git-send-email-wxt@rock-chips.com\0"
  "ref\0CAD=FV=U0FU5P+seYYmJNZmcV1r-N6_UHtMW5LuVGM-NyPER8BQ@mail.gmail.com\0"
- "ref\0CAD=FV=U0FU5P+seYYmJNZmcV1r-N6_UHtMW5LuVGM-NyPER8BQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0"
- "From\0Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0"
- "Subject\0Re: [PATCH v2] arm64: dts: rockchip: add the power domain node for rk3399\0"
+ "From\0wxt@rock-chips.com (Caesar Wang)\0"
+ "Subject\0[PATCH v2] arm64: dts: rockchip: add the power domain node for rk3399\0"
  "Date\0Sat, 02 Jul 2016 09:34:49 +0800\0"
- "To\0Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>"
- " \345\220\264\350\211\257\345\263\260 <william.wu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0"
- "Cc\0Tao Huang <huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org>"
- " Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>"
-  Elaine Zhang <zhangqing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
-  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
-  open list:ARM/Rockchip SoC... <linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
-  Eddie Cai <eddie.cai-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
-  linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
- " Caesar Wang <wxt-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "\n"
- "On 2016\345\271\26407\346\234\21002\346\227\245 00:56, Doug Anderson wrote:\n"
+ "On 2016?07?02? 00:56, Doug Anderson wrote:\n"
  "> Caesar\n"
  ">\n"
  "> On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang <wxt@rock-chips.com> wrote:\n"
@@ -62,9 +52,9 @@
  "That's seem the gmac driver can't handle the power domain enough.\n"
  "--\n"
  "\n"
- "Frankly, I'm no test the GMAC\357\274\214then this patch should support most of \n"
+ "Frankly, I'm no test the GMAC?then this patch should support most of \n"
  "devices.\n"
- "We can send another patch to support it if someone\357\274\210usb/gmac) can handle \n"
+ "We can send another patch to support it if someone?usb/gmac) can handle \n"
  "the power domain.\n"
  "\n"
  ">\n"
@@ -73,12 +63,12 @@
  ">\n"
  ">\n"
  "\n"
- "willam@RK, what's think of it\357\274\237\n"
+ "willam at RK, what's think of it?\n"
  "\n"
  ">> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>\n"
  ">> Signed-off-by: Caesar Wang <wxt@rock-chips.com>\n"
- ">> Cc: linux-arm-kernel@lists.infradead.org\n"
- ">> Cc: linux-rockchip@lists.infradead.org\n"
+ ">> Cc: linux-arm-kernel at lists.infradead.org\n"
+ ">> Cc: linux-rockchip at lists.infradead.org\n"
  ">> Cc: Heiko Stuebner <heiko@sntech.de>\n"
  ">>\n"
  ">> ---\n"
@@ -101,82 +91,82 @@
  ">>                  status = \"disabled\";\n"
  ">>          };\n"
  ">>\n"
- ">> +       qos_hdcp: qos_hdcp@ffa90000 {\n"
+ ">> +       qos_hdcp: qos_hdcp at ffa90000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffa90000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_iep: qos_iep@ffa98000 {\n"
+ ">> +       qos_iep: qos_iep at ffa98000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffa98000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_isp0_m0: qos_isp0_m0@ffaa0000 {\n"
+ ">> +       qos_isp0_m0: qos_isp0_m0 at ffaa0000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffaa0000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_isp0_m1: qos_isp0_m1@ffaa0080 {\n"
+ ">> +       qos_isp0_m1: qos_isp0_m1 at ffaa0080 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffaa0080 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_isp1_m0: qos_isp1_m0@ffaa8000 {\n"
+ ">> +       qos_isp1_m0: qos_isp1_m0 at ffaa8000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffaa8000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_isp1_m1: qos_isp1_m1@ffaa8080 {\n"
+ ">> +       qos_isp1_m1: qos_isp1_m1 at ffaa8080 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffaa8080 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_rga_r: qos_rga_r@ffab0000 {\n"
+ ">> +       qos_rga_r: qos_rga_r at ffab0000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffab0000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_rga_w: qos_rga_w@ffab0080 {\n"
+ ">> +       qos_rga_w: qos_rga_w at ffab0080 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffab0080 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_video_m0: qos_video_m0@ffab8000 {\n"
+ ">> +       qos_video_m0: qos_video_m0 at ffab8000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffab8000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_video_m1_r: qos_video_m1_r@ffac0000 {\n"
+ ">> +       qos_video_m1_r: qos_video_m1_r at ffac0000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffac0000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_video_m1_w: qos_video_m1_w@ffac0080 {\n"
+ ">> +       qos_video_m1_w: qos_video_m1_w at ffac0080 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffac0080 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_vop_big_r: qos_vop_big_r@ffac8000 {\n"
+ ">> +       qos_vop_big_r: qos_vop_big_r at ffac8000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffac8000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_vop_big_w: qos_vop_big_w@ffac8080 {\n"
+ ">> +       qos_vop_big_w: qos_vop_big_w at ffac8080 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffac8080 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_vop_little: qos_vop_little@ffad0000 {\n"
+ ">> +       qos_vop_little: qos_vop_little at ffad0000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffad0000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       qos_gpu: qos_gpu@ffae0000 {\n"
+ ">> +       qos_gpu: qos_gpu at ffae0000 {\n"
  ">> +               compatible = \"syscon\";\n"
  ">> +               reg = <0x0 0xffae0000 0x0 0x20>;\n"
  ">> +       };\n"
  ">> +\n"
- ">> +       pmu: power-management@ff310000 {\n"
+ ">> +       pmu: power-management at ff310000 {\n"
  ">> +               compatible = \"rockchip,rk3399-pmu\", \"syscon\", \"simple-mfd\";\n"
  ">> +               reg = <0x0 0xff310000 0x0 0x1000>;\n"
  ">> +\n"
@@ -195,45 +185,45 @@
  ">> +                       #size-cells = <0>;\n"
  ">> +\n"
  ">> +                       /* These power domains are grouped by VD_LOGIC */\n"
- ">> +                       pd_vio@RK3399_PD_VIO {\n"
+ ">> +                       pd_vio at RK3399_PD_VIO {\n"
  ">> +                               reg = <RK3399_PD_VIO>;\n"
  ">> +                               #address-cells = <1>;\n"
  ">> +                               #size-cells = <0>;\n"
  ">> +\n"
- ">> +                               pd_isp0@RK3399_PD_ISP0 {\n"
+ ">> +                               pd_isp0 at RK3399_PD_ISP0 {\n"
  ">> +                                       reg = <RK3399_PD_ISP0>;\n"
  ">> +                                       clocks = <&cru ACLK_ISP0>,\n"
  ">> +                                                <&cru HCLK_ISP0>;\n"
  ">> +                                       pm_qos = <&qos_isp0_m0>,\n"
  ">> +                                                <&qos_isp0_m1>;\n"
  ">> +                               };\n"
- ">> +                               pd_isp1@RK3399_PD_ISP1 {\n"
+ ">> +                               pd_isp1 at RK3399_PD_ISP1 {\n"
  ">> +                                       reg = <RK3399_PD_ISP1>;\n"
  ">> +                                       clocks = <&cru ACLK_ISP1>,\n"
  ">> +                                                <&cru HCLK_ISP1>;\n"
  ">> +                                       pm_qos = <&qos_isp1_m0>,\n"
  ">> +                                                <&qos_isp1_m1>;\n"
  ">> +                               };\n"
- ">> +                               pd_vo@RK3399_PD_VO {\n"
+ ">> +                               pd_vo at RK3399_PD_VO {\n"
  ">> +                                       reg = <RK3399_PD_VO>;\n"
  ">> +                                       #address-cells = <1>;\n"
  ">> +                                       #size-cells = <0>;\n"
  ">> +\n"
- ">> +                                       pd_vopb@RK3399_PD_VOPB {\n"
+ ">> +                                       pd_vopb at RK3399_PD_VOPB {\n"
  ">> +                                               reg = <RK3399_PD_VOPB>;\n"
  ">> +                                               clocks = <&cru ACLK_VOP0>,\n"
  ">> +                                                        <&cru HCLK_VOP0>;\n"
  ">> +                                               pm_qos = <&qos_vop_big_r>,\n"
  ">> +                                                        <&qos_vop_big_w>;\n"
  ">> +                                       };\n"
- ">> +                                       pd_vopl@RK3399_PD_VOP {\n"
+ ">> +                                       pd_vopl at RK3399_PD_VOP {\n"
  ">> +                                               reg = <RK3399_PD_VOPL>;\n"
  ">> +                                               clocks = <&cru ACLK_VOP1>,\n"
  ">> +                                                        <&cru HCLK_VOP1>;\n"
  ">> +                                               pm_qos = <&qos_vop_little>;\n"
  ">> +                                       };\n"
  ">> +                               };\n"
- ">> +                               pd_hdcp@RK3399_PD_HDCP {\n"
+ ">> +                               pd_hdcp at RK3399_PD_HDCP {\n"
  ">> +                                       reg = <RK3399_PD_HDCP>;\n"
  ">> +                                       clocks = <&cru ACLK_HDCP>,\n"
  ">> +                                                <&cru HCLK_HDCP>,\n"
@@ -250,27 +240,27 @@
  ">> +                       };\n"
  ">> +\n"
  ">> +                       /* These power domains are grouped by VD_CENTER */\n"
- ">> +                       pd_vcodec@RK3399_PD_VCODEC {\n"
+ ">> +                       pd_vcodec at RK3399_PD_VCODEC {\n"
  ">> +                               reg = <RK3399_PD_VCODEC>;\n"
  ">> +                               clocks = <&cru ACLK_VCODEC>,\n"
  ">> +                                        <&cru HCLK_VCODEC>;\n"
  ">> +                               pm_qos = <&qos_video_m0>;\n"
  ">> +                       };\n"
- ">> +                       pd_vdu@RK3399_PD_VDU {\n"
+ ">> +                       pd_vdu at RK3399_PD_VDU {\n"
  ">> +                               reg = <RK3399_PD_VDU>;\n"
  ">> +                               clocks = <&cru ACLK_VDU>,\n"
  ">> +                                        <&cru HCLK_VDU>;\n"
  ">> +                               pm_qos = <&qos_video_m1_r>,\n"
  ">> +                                        <&qos_video_m1_w>;\n"
  ">> +                       };\n"
- ">> +                       pd_rga@RK3399_PD_RGA {\n"
+ ">> +                       pd_rga at RK3399_PD_RGA {\n"
  ">> +                               reg = <RK3399_PD_RGA>;\n"
  ">> +                               clocks = <&cru ACLK_RGA>,\n"
  ">> +                                        <&cru HCLK_RGA>;\n"
  ">> +                               pm_qos = <&qos_rga_r>,\n"
  ">> +                                        <&qos_rga_w>;\n"
  ">> +                       };\n"
- ">> +                       pd_iep@RK3399_PD_IE {\n"
+ ">> +                       pd_iep at RK3399_PD_IE {\n"
  ">> +                               reg = <RK3399_PD_IEP>;\n"
  ">> +                               clocks = <&cru ACLK_IEP>,\n"
  ">> +                                        <&cru HCLK_IEP>;\n"
@@ -282,7 +272,7 @@
  ">\n"
  ">> +\n"
  ">> +                       /* These power domains are grouped by VD_GPU */\n"
- ">> +                       pd_gpu@RK3399_PD_GPU {\n"
+ ">> +                       pd_gpu at RK3399_PD_GPU {\n"
  ">> +                               reg = <RK3399_PD_GPU>;\n"
  ">> +                               clocks = <&cru ACLK_GPU>;\n"
  ">> +                               pm_qos = <&qos_gpu>;\n"
@@ -290,7 +280,7 @@
  ">> +               };\n"
  ">> +       };\n"
  ">> +\n"
- ">>          pmugrf: syscon@ff320000 {\n"
+ ">>          pmugrf: syscon at ff320000 {\n"
  ">>                  compatible = \"rockchip,rk3399-pmugrf\", \"syscon\", \"simple-mfd\";\n"
  ">>                  reg = <0x0 0xff320000 0x0 0x1000>;\n"
  ">> --\n"
@@ -298,18 +288,11 @@
  ">>\n"
  "> _______________________________________________\n"
  "> Linux-rockchip mailing list\n"
- "> Linux-rockchip@lists.infradead.org\n"
+ "> Linux-rockchip at lists.infradead.org\n"
  "> http://lists.infradead.org/mailman/listinfo/linux-rockchip\n"
  "\n"
  "\n"
  "-- \n"
- "caesar wang | software engineer | wxt@rock-chip.com\n"
- "\n"
- "\n"
- "\n"
- "_______________________________________________\n"
- "Linux-rockchip mailing list\n"
- "Linux-rockchip@lists.infradead.org\n"
- http://lists.infradead.org/mailman/listinfo/linux-rockchip
+ caesar wang | software engineer | wxt at rock-chip.com
 
-de99a9e97bace1b6169640f10bdf135e453d91ab539a0e06bf1af77829cea0d9
+ef337e3293b43bd5973fdc122b50f0bd9eaf28a91269ad366c5732cf46636f47
