diff for duplicates of <577737F6.7000008@rock-chips.com>

diff --git a/a/1.txt b/N1/1.txt
index 471b1da..9f2c4b6 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -3,7 +3,7 @@ Dear Caesar & Doug,
 
 On 07/02/2016 09:34 AM, Caesar Wang wrote:
 >
-> On 2016年07月02日 00:56, Doug Anderson wrote:
+> On 2016?07?02? 00:56, Doug Anderson wrote:
 >> Caesar
 >>
 >> On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang <wxt@rock-chips.com> wrote:
@@ -50,9 +50,9 @@ On 07/02/2016 09:34 AM, Caesar Wang wrote:
 > That's seem the gmac driver can't handle the power domain enough.
 > -- 
 >
-> Frankly, I'm no test the GMAC，then this patch should support most of
+> Frankly, I'm no test the GMAC?then this patch should support most of
 > devices.
-> We can send another patch to support it if someone（usb/gmac) can
+> We can send another patch to support it if someone?usb/gmac) can
 > handle the power domain.
 >
 >>
@@ -61,16 +61,16 @@ On 07/02/2016 09:34 AM, Caesar Wang wrote:
 >>
 >>
 >
-> willam@RK, what's think of it？
+> willam at RK, what's think of it?
 RK3399 support XHCI controller, but it's integrated in DWC3 IP core,
 and we don't need to add xhci node separately, but just add dwc3
 node like this:
-usbdrd3_0: usb@fe800000 {
+usbdrd3_0: usb at fe800000 {
 compatible = "rockchip,rk3399-dwc3";
 ......
 ranges;
 status = "disabled";
-usbdrd_dwc3_0: dwc3@fe800000 {
+usbdrd_dwc3_0: dwc3 at fe800000 {
 compatible = "snps,dwc3";
 reg = <0x0 0xfe800000 0x0 0x100000>;
 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
@@ -89,8 +89,8 @@ William Wu
 >
 >>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 >>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
->>> Cc: linux-arm-kernel@lists.infradead.org
->>> Cc: linux-rockchip@lists.infradead.org
+>>> Cc: linux-arm-kernel at lists.infradead.org
+>>> Cc: linux-rockchip at lists.infradead.org
 >>> Cc: Heiko Stuebner <heiko@sntech.de>
 >>>
 >>> ---
@@ -115,82 +115,82 @@ William Wu
 >>> status = "disabled";
 >>> };
 >>>
->>> + qos_hdcp: qos_hdcp@ffa90000 {
+>>> + qos_hdcp: qos_hdcp at ffa90000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffa90000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_iep: qos_iep@ffa98000 {
+>>> + qos_iep: qos_iep at ffa98000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffa98000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_isp0_m0: qos_isp0_m0@ffaa0000 {
+>>> + qos_isp0_m0: qos_isp0_m0 at ffaa0000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffaa0000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_isp0_m1: qos_isp0_m1@ffaa0080 {
+>>> + qos_isp0_m1: qos_isp0_m1 at ffaa0080 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffaa0080 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_isp1_m0: qos_isp1_m0@ffaa8000 {
+>>> + qos_isp1_m0: qos_isp1_m0 at ffaa8000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffaa8000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_isp1_m1: qos_isp1_m1@ffaa8080 {
+>>> + qos_isp1_m1: qos_isp1_m1 at ffaa8080 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffaa8080 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_rga_r: qos_rga_r@ffab0000 {
+>>> + qos_rga_r: qos_rga_r at ffab0000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffab0000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_rga_w: qos_rga_w@ffab0080 {
+>>> + qos_rga_w: qos_rga_w at ffab0080 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffab0080 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_video_m0: qos_video_m0@ffab8000 {
+>>> + qos_video_m0: qos_video_m0 at ffab8000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffab8000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_video_m1_r: qos_video_m1_r@ffac0000 {
+>>> + qos_video_m1_r: qos_video_m1_r at ffac0000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffac0000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_video_m1_w: qos_video_m1_w@ffac0080 {
+>>> + qos_video_m1_w: qos_video_m1_w at ffac0080 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffac0080 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_vop_big_r: qos_vop_big_r@ffac8000 {
+>>> + qos_vop_big_r: qos_vop_big_r at ffac8000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffac8000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_vop_big_w: qos_vop_big_w@ffac8080 {
+>>> + qos_vop_big_w: qos_vop_big_w at ffac8080 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffac8080 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_vop_little: qos_vop_little@ffad0000 {
+>>> + qos_vop_little: qos_vop_little at ffad0000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffad0000 0x0 0x20>;
 >>> + };
 >>> +
->>> + qos_gpu: qos_gpu@ffae0000 {
+>>> + qos_gpu: qos_gpu at ffae0000 {
 >>> + compatible = "syscon";
 >>> + reg = <0x0 0xffae0000 0x0 0x20>;
 >>> + };
 >>> +
->>> + pmu: power-management@ff310000 {
+>>> + pmu: power-management at ff310000 {
 >>> + compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 >>> + reg = <0x0 0xff310000 0x0 0x1000>;
 >>> +
@@ -209,45 +209,45 @@ William Wu
 >>> + #size-cells = <0>;
 >>> +
 >>> + /* These power domains are grouped by VD_LOGIC */
->>> + pd_vio@RK3399_PD_VIO {
+>>> + pd_vio at RK3399_PD_VIO {
 >>> + reg = <RK3399_PD_VIO>;
 >>> + #address-cells = <1>;
 >>> + #size-cells = <0>;
 >>> +
->>> + pd_isp0@RK3399_PD_ISP0 {
+>>> + pd_isp0 at RK3399_PD_ISP0 {
 >>> + reg = <RK3399_PD_ISP0>;
 >>> + clocks = <&cru ACLK_ISP0>,
 >>> + <&cru HCLK_ISP0>;
 >>> + pm_qos = <&qos_isp0_m0>,
 >>> + <&qos_isp0_m1>;
 >>> + };
->>> + pd_isp1@RK3399_PD_ISP1 {
+>>> + pd_isp1 at RK3399_PD_ISP1 {
 >>> + reg = <RK3399_PD_ISP1>;
 >>> + clocks = <&cru ACLK_ISP1>,
 >>> + <&cru HCLK_ISP1>;
 >>> + pm_qos = <&qos_isp1_m0>,
 >>> + <&qos_isp1_m1>;
 >>> + };
->>> + pd_vo@RK3399_PD_VO {
+>>> + pd_vo at RK3399_PD_VO {
 >>> + reg = <RK3399_PD_VO>;
 >>> + #address-cells = <1>;
 >>> + #size-cells = <0>;
 >>> +
->>> + pd_vopb@RK3399_PD_VOPB {
+>>> + pd_vopb at RK3399_PD_VOPB {
 >>> + reg = <RK3399_PD_VOPB>;
 >>> + clocks = <&cru ACLK_VOP0>,
 >>> + <&cru HCLK_VOP0>;
 >>> + pm_qos = <&qos_vop_big_r>,
 >>> + <&qos_vop_big_w>;
 >>> + };
->>> + pd_vopl@RK3399_PD_VOP {
+>>> + pd_vopl at RK3399_PD_VOP {
 >>> + reg = <RK3399_PD_VOPL>;
 >>> + clocks = <&cru ACLK_VOP1>,
 >>> + <&cru HCLK_VOP1>;
 >>> + pm_qos = <&qos_vop_little>;
 >>> + };
 >>> + };
->>> + pd_hdcp@RK3399_PD_HDCP {
+>>> + pd_hdcp at RK3399_PD_HDCP {
 >>> + reg = <RK3399_PD_HDCP>;
 >>> + clocks = <&cru ACLK_HDCP>,
 >>> + <&cru HCLK_HDCP>,
@@ -264,27 +264,27 @@ William Wu
 >>> + };
 >>> +
 >>> + /* These power domains are grouped by VD_CENTER */
->>> + pd_vcodec@RK3399_PD_VCODEC {
+>>> + pd_vcodec at RK3399_PD_VCODEC {
 >>> + reg = <RK3399_PD_VCODEC>;
 >>> + clocks = <&cru ACLK_VCODEC>,
 >>> + <&cru HCLK_VCODEC>;
 >>> + pm_qos = <&qos_video_m0>;
 >>> + };
->>> + pd_vdu@RK3399_PD_VDU {
+>>> + pd_vdu at RK3399_PD_VDU {
 >>> + reg = <RK3399_PD_VDU>;
 >>> + clocks = <&cru ACLK_VDU>,
 >>> + <&cru HCLK_VDU>;
 >>> + pm_qos = <&qos_video_m1_r>,
 >>> + <&qos_video_m1_w>;
 >>> + };
->>> + pd_rga@RK3399_PD_RGA {
+>>> + pd_rga at RK3399_PD_RGA {
 >>> + reg = <RK3399_PD_RGA>;
 >>> + clocks = <&cru ACLK_RGA>,
 >>> + <&cru HCLK_RGA>;
 >>> + pm_qos = <&qos_rga_r>,
 >>> + <&qos_rga_w>;
 >>> + };
->>> + pd_iep@RK3399_PD_IE {
+>>> + pd_iep at RK3399_PD_IE {
 >>> + reg = <RK3399_PD_IEP>;
 >>> + clocks = <&cru ACLK_IEP>,
 >>> + <&cru HCLK_IEP>;
@@ -296,7 +296,7 @@ William Wu
 >>
 >>> +
 >>> + /* These power domains are grouped by VD_GPU */
->>> + pd_gpu@RK3399_PD_GPU {
+>>> + pd_gpu at RK3399_PD_GPU {
 >>> + reg = <RK3399_PD_GPU>;
 >>> + clocks = <&cru ACLK_GPU>;
 >>> + pm_qos = <&qos_gpu>;
@@ -304,7 +304,7 @@ William Wu
 >>> + };
 >>> + };
 >>> +
->>> pmugrf: syscon@ff320000 {
+>>> pmugrf: syscon at ff320000 {
 >>> compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
 >>> reg = <0x0 0xff320000 0x0 0x1000>;
 >>> -- 
@@ -312,7 +312,7 @@ William Wu
 >>>
 >> _______________________________________________
 >> Linux-rockchip mailing list
->> Linux-rockchip@lists.infradead.org
+>> Linux-rockchip at lists.infradead.org
 >> http://lists.infradead.org/mailman/listinfo/linux-rockchip
 >
 >
diff --git a/a/content_digest b/N1/content_digest
index ab3c038..cb2a6f7 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,18 +1,10 @@
  "ref\01467347575-11806-1-git-send-email-wxt@rock-chips.com\0"
  "ref\0CAD=FV=U0FU5P+seYYmJNZmcV1r-N6_UHtMW5LuVGM-NyPER8BQ@mail.gmail.com\0"
  "ref\057771A39.8060606@rock-chips.com\0"
- "From\0William Wu <william.wu@rock-chips.com>\0"
- "Subject\0Re: [PATCH v2] arm64: dts: rockchip: add the power domain node for rk3399\0"
+ "From\0william.wu@rock-chips.com (William Wu)\0"
+ "Subject\0[PATCH v2] arm64: dts: rockchip: add the power domain node for rk3399\0"
  "Date\0Sat, 02 Jul 2016 11:41:42 +0800\0"
- "To\0Caesar Wang <wxt@rock-chips.com>"
- " Doug Anderson <dianders@chromium.org>\0"
- "Cc\0Tao Huang <huangtao@rock-chips.com>"
- " Heiko St\303\274bner <heiko@sntech.de>"
-  Elaine Zhang <zhangqing@rock-chips.com>
-  linux-kernel@vger.kernel.org <linux-kernel@vger.kernel.org>
-  open list:ARM/Rockchip SoC... <linux-rockchip@lists.infradead.org>
-  Eddie Cai <eddie.cai@rock-chips.com>
- " linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org>\0"
+ "To\0linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
  "Dear Caesar & Doug,\n"
@@ -20,7 +12,7 @@
  "\n"
  "On 07/02/2016 09:34 AM, Caesar Wang wrote:\n"
  ">\n"
- "> On 2016\345\271\26407\346\234\21002\346\227\245 00:56, Doug Anderson wrote:\n"
+ "> On 2016?07?02? 00:56, Doug Anderson wrote:\n"
  ">> Caesar\n"
  ">>\n"
  ">> On Thu, Jun 30, 2016 at 9:32 PM, Caesar Wang <wxt@rock-chips.com> wrote:\n"
@@ -67,9 +59,9 @@
  "> That's seem the gmac driver can't handle the power domain enough.\n"
  "> -- \n"
  ">\n"
- "> Frankly, I'm no test the GMAC\357\274\214then this patch should support most of\n"
+ "> Frankly, I'm no test the GMAC?then this patch should support most of\n"
  "> devices.\n"
- "> We can send another patch to support it if someone\357\274\210usb/gmac) can\n"
+ "> We can send another patch to support it if someone?usb/gmac) can\n"
  "> handle the power domain.\n"
  ">\n"
  ">>\n"
@@ -78,16 +70,16 @@
  ">>\n"
  ">>\n"
  ">\n"
- "> willam@RK, what's think of it\357\274\237\n"
+ "> willam at RK, what's think of it?\n"
  "RK3399 support XHCI controller, but it's integrated in DWC3 IP core,\n"
  "and we don't need to add xhci node separately, but just add dwc3\n"
  "node like this:\n"
- "usbdrd3_0: usb@fe800000 {\n"
+ "usbdrd3_0: usb at fe800000 {\n"
  "compatible = \"rockchip,rk3399-dwc3\";\n"
  "......\n"
  "ranges;\n"
  "status = \"disabled\";\n"
- "usbdrd_dwc3_0: dwc3@fe800000 {\n"
+ "usbdrd_dwc3_0: dwc3 at fe800000 {\n"
  "compatible = \"snps,dwc3\";\n"
  "reg = <0x0 0xfe800000 0x0 0x100000>;\n"
  "interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;\n"
@@ -106,8 +98,8 @@
  ">\n"
  ">>> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>\n"
  ">>> Signed-off-by: Caesar Wang <wxt@rock-chips.com>\n"
- ">>> Cc: linux-arm-kernel@lists.infradead.org\n"
- ">>> Cc: linux-rockchip@lists.infradead.org\n"
+ ">>> Cc: linux-arm-kernel at lists.infradead.org\n"
+ ">>> Cc: linux-rockchip at lists.infradead.org\n"
  ">>> Cc: Heiko Stuebner <heiko@sntech.de>\n"
  ">>>\n"
  ">>> ---\n"
@@ -132,82 +124,82 @@
  ">>> status = \"disabled\";\n"
  ">>> };\n"
  ">>>\n"
- ">>> + qos_hdcp: qos_hdcp@ffa90000 {\n"
+ ">>> + qos_hdcp: qos_hdcp at ffa90000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffa90000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_iep: qos_iep@ffa98000 {\n"
+ ">>> + qos_iep: qos_iep at ffa98000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffa98000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_isp0_m0: qos_isp0_m0@ffaa0000 {\n"
+ ">>> + qos_isp0_m0: qos_isp0_m0 at ffaa0000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffaa0000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_isp0_m1: qos_isp0_m1@ffaa0080 {\n"
+ ">>> + qos_isp0_m1: qos_isp0_m1 at ffaa0080 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffaa0080 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_isp1_m0: qos_isp1_m0@ffaa8000 {\n"
+ ">>> + qos_isp1_m0: qos_isp1_m0 at ffaa8000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffaa8000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_isp1_m1: qos_isp1_m1@ffaa8080 {\n"
+ ">>> + qos_isp1_m1: qos_isp1_m1 at ffaa8080 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffaa8080 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_rga_r: qos_rga_r@ffab0000 {\n"
+ ">>> + qos_rga_r: qos_rga_r at ffab0000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffab0000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_rga_w: qos_rga_w@ffab0080 {\n"
+ ">>> + qos_rga_w: qos_rga_w at ffab0080 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffab0080 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_video_m0: qos_video_m0@ffab8000 {\n"
+ ">>> + qos_video_m0: qos_video_m0 at ffab8000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffab8000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_video_m1_r: qos_video_m1_r@ffac0000 {\n"
+ ">>> + qos_video_m1_r: qos_video_m1_r at ffac0000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffac0000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_video_m1_w: qos_video_m1_w@ffac0080 {\n"
+ ">>> + qos_video_m1_w: qos_video_m1_w at ffac0080 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffac0080 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_vop_big_r: qos_vop_big_r@ffac8000 {\n"
+ ">>> + qos_vop_big_r: qos_vop_big_r at ffac8000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffac8000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_vop_big_w: qos_vop_big_w@ffac8080 {\n"
+ ">>> + qos_vop_big_w: qos_vop_big_w at ffac8080 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffac8080 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_vop_little: qos_vop_little@ffad0000 {\n"
+ ">>> + qos_vop_little: qos_vop_little at ffad0000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffad0000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + qos_gpu: qos_gpu@ffae0000 {\n"
+ ">>> + qos_gpu: qos_gpu at ffae0000 {\n"
  ">>> + compatible = \"syscon\";\n"
  ">>> + reg = <0x0 0xffae0000 0x0 0x20>;\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> + pmu: power-management@ff310000 {\n"
+ ">>> + pmu: power-management at ff310000 {\n"
  ">>> + compatible = \"rockchip,rk3399-pmu\", \"syscon\", \"simple-mfd\";\n"
  ">>> + reg = <0x0 0xff310000 0x0 0x1000>;\n"
  ">>> +\n"
@@ -226,45 +218,45 @@
  ">>> + #size-cells = <0>;\n"
  ">>> +\n"
  ">>> + /* These power domains are grouped by VD_LOGIC */\n"
- ">>> + pd_vio@RK3399_PD_VIO {\n"
+ ">>> + pd_vio at RK3399_PD_VIO {\n"
  ">>> + reg = <RK3399_PD_VIO>;\n"
  ">>> + #address-cells = <1>;\n"
  ">>> + #size-cells = <0>;\n"
  ">>> +\n"
- ">>> + pd_isp0@RK3399_PD_ISP0 {\n"
+ ">>> + pd_isp0 at RK3399_PD_ISP0 {\n"
  ">>> + reg = <RK3399_PD_ISP0>;\n"
  ">>> + clocks = <&cru ACLK_ISP0>,\n"
  ">>> + <&cru HCLK_ISP0>;\n"
  ">>> + pm_qos = <&qos_isp0_m0>,\n"
  ">>> + <&qos_isp0_m1>;\n"
  ">>> + };\n"
- ">>> + pd_isp1@RK3399_PD_ISP1 {\n"
+ ">>> + pd_isp1 at RK3399_PD_ISP1 {\n"
  ">>> + reg = <RK3399_PD_ISP1>;\n"
  ">>> + clocks = <&cru ACLK_ISP1>,\n"
  ">>> + <&cru HCLK_ISP1>;\n"
  ">>> + pm_qos = <&qos_isp1_m0>,\n"
  ">>> + <&qos_isp1_m1>;\n"
  ">>> + };\n"
- ">>> + pd_vo@RK3399_PD_VO {\n"
+ ">>> + pd_vo at RK3399_PD_VO {\n"
  ">>> + reg = <RK3399_PD_VO>;\n"
  ">>> + #address-cells = <1>;\n"
  ">>> + #size-cells = <0>;\n"
  ">>> +\n"
- ">>> + pd_vopb@RK3399_PD_VOPB {\n"
+ ">>> + pd_vopb at RK3399_PD_VOPB {\n"
  ">>> + reg = <RK3399_PD_VOPB>;\n"
  ">>> + clocks = <&cru ACLK_VOP0>,\n"
  ">>> + <&cru HCLK_VOP0>;\n"
  ">>> + pm_qos = <&qos_vop_big_r>,\n"
  ">>> + <&qos_vop_big_w>;\n"
  ">>> + };\n"
- ">>> + pd_vopl@RK3399_PD_VOP {\n"
+ ">>> + pd_vopl at RK3399_PD_VOP {\n"
  ">>> + reg = <RK3399_PD_VOPL>;\n"
  ">>> + clocks = <&cru ACLK_VOP1>,\n"
  ">>> + <&cru HCLK_VOP1>;\n"
  ">>> + pm_qos = <&qos_vop_little>;\n"
  ">>> + };\n"
  ">>> + };\n"
- ">>> + pd_hdcp@RK3399_PD_HDCP {\n"
+ ">>> + pd_hdcp at RK3399_PD_HDCP {\n"
  ">>> + reg = <RK3399_PD_HDCP>;\n"
  ">>> + clocks = <&cru ACLK_HDCP>,\n"
  ">>> + <&cru HCLK_HDCP>,\n"
@@ -281,27 +273,27 @@
  ">>> + };\n"
  ">>> +\n"
  ">>> + /* These power domains are grouped by VD_CENTER */\n"
- ">>> + pd_vcodec@RK3399_PD_VCODEC {\n"
+ ">>> + pd_vcodec at RK3399_PD_VCODEC {\n"
  ">>> + reg = <RK3399_PD_VCODEC>;\n"
  ">>> + clocks = <&cru ACLK_VCODEC>,\n"
  ">>> + <&cru HCLK_VCODEC>;\n"
  ">>> + pm_qos = <&qos_video_m0>;\n"
  ">>> + };\n"
- ">>> + pd_vdu@RK3399_PD_VDU {\n"
+ ">>> + pd_vdu at RK3399_PD_VDU {\n"
  ">>> + reg = <RK3399_PD_VDU>;\n"
  ">>> + clocks = <&cru ACLK_VDU>,\n"
  ">>> + <&cru HCLK_VDU>;\n"
  ">>> + pm_qos = <&qos_video_m1_r>,\n"
  ">>> + <&qos_video_m1_w>;\n"
  ">>> + };\n"
- ">>> + pd_rga@RK3399_PD_RGA {\n"
+ ">>> + pd_rga at RK3399_PD_RGA {\n"
  ">>> + reg = <RK3399_PD_RGA>;\n"
  ">>> + clocks = <&cru ACLK_RGA>,\n"
  ">>> + <&cru HCLK_RGA>;\n"
  ">>> + pm_qos = <&qos_rga_r>,\n"
  ">>> + <&qos_rga_w>;\n"
  ">>> + };\n"
- ">>> + pd_iep@RK3399_PD_IE {\n"
+ ">>> + pd_iep at RK3399_PD_IE {\n"
  ">>> + reg = <RK3399_PD_IEP>;\n"
  ">>> + clocks = <&cru ACLK_IEP>,\n"
  ">>> + <&cru HCLK_IEP>;\n"
@@ -313,7 +305,7 @@
  ">>\n"
  ">>> +\n"
  ">>> + /* These power domains are grouped by VD_GPU */\n"
- ">>> + pd_gpu@RK3399_PD_GPU {\n"
+ ">>> + pd_gpu at RK3399_PD_GPU {\n"
  ">>> + reg = <RK3399_PD_GPU>;\n"
  ">>> + clocks = <&cru ACLK_GPU>;\n"
  ">>> + pm_qos = <&qos_gpu>;\n"
@@ -321,7 +313,7 @@
  ">>> + };\n"
  ">>> + };\n"
  ">>> +\n"
- ">>> pmugrf: syscon@ff320000 {\n"
+ ">>> pmugrf: syscon at ff320000 {\n"
  ">>> compatible = \"rockchip,rk3399-pmugrf\", \"syscon\", \"simple-mfd\";\n"
  ">>> reg = <0x0 0xff320000 0x0 0x1000>;\n"
  ">>> -- \n"
@@ -329,9 +321,9 @@
  ">>>\n"
  ">> _______________________________________________\n"
  ">> Linux-rockchip mailing list\n"
- ">> Linux-rockchip@lists.infradead.org\n"
+ ">> Linux-rockchip at lists.infradead.org\n"
  ">> http://lists.infradead.org/mailman/listinfo/linux-rockchip\n"
  ">\n"
  >
 
-a873a2e866278c3bb3404dc54897fa226ac890b1e64fa42db2cea8928845db82
+406ca89190c01d2996381158e1575b6eafaa484d3e91a8021f854664790333fe
