Re: [PATCH 09/14] cxl: Add preliminary workaround for CX4 interrupt limitation

[Frederic Barrat <fbarrat@linux.vnet.ibm.com>]

Le 04/07/2016 15:22, Ian Munsie a écrit :
> From: Ian Munsie <imunsie@au1.ibm.com>
>
> The Mellanox CX4 has a hardware limitation where only 4 bits of the
> AFU interrupt number can be passed to the XSL when sending an interrupt,
> limiting it to only 15 interrupts per context (AFU interrupt number 0 is
> invalid).
>
> In order to overcome this, we will allocate additional contexts linked
> to the default context as extra address space for the extra interrupts -
> this will be implemented in the next patch.
>
> This patch adds the preliminary support to allow this, by way of adding
> a linked list in the context structure that we use to keep track of the
> contexts dedicated to interrupts, and an API to simultaneously iterate
> over the related context structures, AFU interrupt numbers and hardware
> interrupt numbers. The point of using a single API to iterate these is
> to hide some of the details of the iteration from external code, and to
> reduce the number of APIs that need to be exported via base.c to allow
> built in code to call.
>

Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Just one typo below


> diff --git a/include/misc/cxl.h b/include/misc/cxl.h
> index fc07ed4..ed81a17 100644
> --- a/include/misc/cxl.h
> +++ b/include/misc/cxl.h
> @@ -178,6 +178,15 @@ int cxl_set_max_irqs_per_process(struct pci_dev *dev, int irqs);
>   int cxl_get_max_irqs_per_process(struct pci_dev *dev);
>
>   /*
> + * Use to simultaneously iterate over hardware interrupt numbers, contexts and
> + * afu interrupt numbers allocated for the device via pci_enable_msix_range and
> + * is a useful convinience function when working with hardware that has

convenience