diff for duplicates of <577DF5D4.4010008@nvidia.com> diff --git a/a/1.txt b/N1/1.txt index e672efd..d0ff80d 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On 07/06/2016 07:42 PM, Alexandre Courbot wrote: -> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: +> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl@nvidia.com> wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management, clock >> management, and reset control tasks from the CPU. The binding document @@ -7,7 +7,7 @@ On 07/06/2016 07:42 PM, Alexandre Courbot wrote: >> which can create the interprocessor communication (IPC) between the CPU >> and BPMP. >> ->> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +>> Signed-off-by: Joseph Lo <josephl@nvidia.com> >> --- >> Changes in V2: >> - update the message that the BPMP is clock and reset control provider @@ -75,12 +75,12 @@ On 07/06/2016 07:42 PM, Alexandre Courbot wrote: >> + >> +Example: >> + ->> +hsp_top0: hsp@03c00000 { +>> +hsp_top0: hsp at 03c00000 { >> + ... >> + #mbox-cells = <1>; >> +}; >> + ->> +sysram@30000000 { +>> +sysram at 30000000 { >> + compatible = "nvidia,tegra186-sysram", "mmio-ram"; > > Shouldn't the second compatible be "mmio-sram"? diff --git a/a/content_digest b/N1/content_digest index 4e1af25..6d96c67 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,28 +1,14 @@ "ref\020160705090431.5852-1-josephl@nvidia.com\0" "ref\020160705090431.5852-4-josephl@nvidia.com\0" "ref\0CAAVeFuJwhQ=L803W7K+e5_VUKrfB2NyCz+WMR91QuvKgmv1ofw@mail.gmail.com\0" - "ref\0CAAVeFuJwhQ=L803W7K+e5_VUKrfB2NyCz+WMR91QuvKgmv1ofw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" - "From\0Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" - "Subject\0Re: [PATCH V2 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP\0" + "From\0josephl@nvidia.com (Joseph Lo)\0" + "Subject\0[PATCH V2 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP\0" "Date\0Thu, 7 Jul 2016 14:25:24 +0800\0" - "To\0Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Matthew Longnecker <MLongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Linux Kernel Mailing List <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> - " Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On 07/06/2016 07:42 PM, Alexandre Courbot wrote:\n" - "> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:\n" + "> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl@nvidia.com> wrote:\n" ">> The BPMP is a specific processor in Tegra chip, which is designed for\n" ">> booting process handling and offloading the power management, clock\n" ">> management, and reset control tasks from the CPU. The binding document\n" @@ -30,7 +16,7 @@ ">> which can create the interprocessor communication (IPC) between the CPU\n" ">> and BPMP.\n" ">>\n" - ">> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + ">> Signed-off-by: Joseph Lo <josephl@nvidia.com>\n" ">> ---\n" ">> Changes in V2:\n" ">> - update the message that the BPMP is clock and reset control provider\n" @@ -98,12 +84,12 @@ ">> +\n" ">> +Example:\n" ">> +\n" - ">> +hsp_top0: hsp@03c00000 {\n" + ">> +hsp_top0: hsp at 03c00000 {\n" ">> + ...\n" ">> + #mbox-cells = <1>;\n" ">> +};\n" ">> +\n" - ">> +sysram@30000000 {\n" + ">> +sysram at 30000000 {\n" ">> + compatible = \"nvidia,tegra186-sysram\", \"mmio-ram\";\n" ">\n" "> Shouldn't the second compatible be \"mmio-sram\"?\n" @@ -116,4 +102,4 @@ "Thanks,\n" -Joseph -ba371f628cd599618bfa5d2bd512bb251d228de441b63b22ce1f2eb3db942c64 +cf8b5105356e571432a4d8133f688e08c3e1e85c3717d72bca43983e655883ff
diff --git a/a/1.txt b/N2/1.txt index e672efd..c380e73 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,5 +1,5 @@ On 07/06/2016 07:42 PM, Alexandre Courbot wrote: -> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote: +> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl@nvidia.com> wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management, clock >> management, and reset control tasks from the CPU. The binding document @@ -7,7 +7,7 @@ On 07/06/2016 07:42 PM, Alexandre Courbot wrote: >> which can create the interprocessor communication (IPC) between the CPU >> and BPMP. >> ->> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> +>> Signed-off-by: Joseph Lo <josephl@nvidia.com> >> --- >> Changes in V2: >> - update the message that the BPMP is clock and reset control provider diff --git a/a/content_digest b/N2/content_digest index 4e1af25..7cd78af 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,28 +1,27 @@ "ref\020160705090431.5852-1-josephl@nvidia.com\0" "ref\020160705090431.5852-4-josephl@nvidia.com\0" "ref\0CAAVeFuJwhQ=L803W7K+e5_VUKrfB2NyCz+WMR91QuvKgmv1ofw@mail.gmail.com\0" - "ref\0CAAVeFuJwhQ=L803W7K+e5_VUKrfB2NyCz+WMR91QuvKgmv1ofw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" - "From\0Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\0" + "From\0Joseph Lo <josephl@nvidia.com>\0" "Subject\0Re: [PATCH V2 03/10] Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP\0" "Date\0Thu, 7 Jul 2016 14:25:24 +0800\0" - "To\0Alexandre Courbot <gnurou-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>\0" - "Cc\0Stephen Warren <swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>" - Thierry Reding <thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org> - Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> - Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> - Peter De Schrijver <pdeschrijver-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - Matthew Longnecker <MLongnecker-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Jassi Brar <jassisinghbrar-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> - Linux Kernel Mailing List <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org> - " Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" + "To\0Alexandre Courbot <gnurou@gmail.com>\0" + "Cc\0Stephen Warren <swarren@wwwdotorg.org>" + Thierry Reding <thierry.reding@gmail.com> + linux-tegra@vger.kernel.org <linux-tegra@vger.kernel.org> + linux-arm-kernel@lists.infradead.org <linux-arm-kernel@lists.infradead.org> + Rob Herring <robh+dt@kernel.org> + Mark Rutland <mark.rutland@arm.com> + Peter De Schrijver <pdeschrijver@nvidia.com> + Matthew Longnecker <MLongnecker@nvidia.com> + devicetree@vger.kernel.org <devicetree@vger.kernel.org> + Jassi Brar <jassisinghbrar@gmail.com> + Linux Kernel Mailing List <linux-kernel@vger.kernel.org> + Catalin Marinas <catalin.marinas@arm.com> + " Will Deacon <will.deacon@arm.com>\0" "\00:1\0" "b\0" "On 07/06/2016 07:42 PM, Alexandre Courbot wrote:\n" - "> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org> wrote:\n" + "> On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo <josephl@nvidia.com> wrote:\n" ">> The BPMP is a specific processor in Tegra chip, which is designed for\n" ">> booting process handling and offloading the power management, clock\n" ">> management, and reset control tasks from the CPU. The binding document\n" @@ -30,7 +29,7 @@ ">> which can create the interprocessor communication (IPC) between the CPU\n" ">> and BPMP.\n" ">>\n" - ">> Signed-off-by: Joseph Lo <josephl-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>\n" + ">> Signed-off-by: Joseph Lo <josephl@nvidia.com>\n" ">> ---\n" ">> Changes in V2:\n" ">> - update the message that the BPMP is clock and reset control provider\n" @@ -116,4 +115,4 @@ "Thanks,\n" -Joseph -ba371f628cd599618bfa5d2bd512bb251d228de441b63b22ce1f2eb3db942c64 +1a595923dd24301fdcda799d067c75618007ae29aa8c84c4aa00ad04736cd0af
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