From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mario Kleiner Subject: Re: [PATCH 2/2] drm/vc4: Squash commit for Mario's precise vblank timestamping. Date: Sat, 9 Jul 2016 19:09:04 +0200 Message-ID: <57812FB0.6000207@gmail.com> References: <1466662670-9884-2-git-send-email-mario.kleiner.de@gmail.com> <1468003498-2476-1-git-send-email-eric@anholt.net> <1468003498-2476-2-git-send-email-eric@anholt.net> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56BF66E10F for ; Sat, 9 Jul 2016 17:09:09 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id k123so11559917wme.2 for ; Sat, 09 Jul 2016 10:09:09 -0700 (PDT) In-Reply-To: <1468003498-2476-2-git-send-email-eric@anholt.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Eric Anholt , dri-devel@lists.freedesktop.org Cc: linux-kernel@vger.kernel.org List-Id: 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S1756839AbcGIRJQ (ORCPT ); Sat, 9 Jul 2016 13:09:16 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:36326 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751897AbcGIRJJ (ORCPT ); Sat, 9 Jul 2016 13:09:09 -0400 Subject: Re: [PATCH 2/2] drm/vc4: Squash commit for Mario's precise vblank timestamping. To: Eric Anholt , dri-devel@lists.freedesktop.org References: <1466662670-9884-2-git-send-email-mario.kleiner.de@gmail.com> <1468003498-2476-1-git-send-email-eric@anholt.net> <1468003498-2476-2-git-send-email-eric@anholt.net> Cc: linux-kernel@vger.kernel.org, Mario Kleiner From: Mario Kleiner Message-ID: <57812FB0.6000207@gmail.com> Date: Sat, 9 Jul 2016 19:09:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1468003498-2476-2-git-send-email-eric@anholt.net> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Eric, thanks for all the infos and help! Both your patches look good and i have successfully tested them on top of with my vblank timestamping patch. So for both: Reviewed-and-tested-by: Mario Kleiner Will you squash 2/2 into my patch or should i resend my patch with yours squashed in? thanks, -mario On 07/08/2016 08:44 PM, Eric Anholt wrote: > Read out the DISPBASE registers to decide on the FIFO size. > > Signed-off-by: Eric Anholt > --- > > Mario: How about this for a squash into your commit? Here are the > values I dumped for cob_size: > > [ 2.148314] [drm] Scaler 0 size 5232 > [ 2.162239] [drm] Scaler 2 size 2048 > [ 2.172957] [drm] Scaler 1 size 13456 > > drivers/gpu/drm/vc4/vc4_crtc.c | 23 +++++++++++++++++++++-- > drivers/gpu/drm/vc4/vc4_regs.h | 18 +++++++++++++++++- > 2 files changed, 38 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c > index baf962bce063..3b7db17c356d 100644 > --- a/drivers/gpu/drm/vc4/vc4_crtc.c > +++ b/drivers/gpu/drm/vc4/vc4_crtc.c > @@ -55,6 +55,8 @@ struct vc4_crtc { > u8 lut_r[256]; > u8 lut_g[256]; > u8 lut_b[256]; > + /* Size in pixels of the COB memory allocated to this CRTC. */ > + u32 cob_size; > > struct drm_pending_vblank_event *event; > }; > @@ -195,8 +197,7 @@ int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, > *hpos = 0; > > /* This is the offset we need for translating hvs -> pv scanout pos. */ > - /* XXX Find proper formula from hw docs instead of guesstimating? */ > - fifo_lines = 2048 * 7 / mode->crtc_hdisplay; > + fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay; > > if (fifo_lines > 0) > ret |= DRM_SCANOUTPOS_VALID; > @@ -873,6 +874,22 @@ static void vc4_set_crtc_possible_masks(struct drm_device *drm, > } > } > > +static void > +vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc) > +{ > + struct drm_device *drm = vc4_crtc->base.dev; > + struct vc4_dev *vc4 = to_vc4_dev(drm); > + u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel)); > + /* Top/base are supposed to be 4-pixel aligned, but the > + * Raspberry Pi firmware fills the low bits (which are > + * presumably ignored). > + */ > + u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; > + u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; > + > + vc4_crtc->cob_size = top - base + 4; > +} > + > static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) > { > struct platform_device *pdev = to_platform_device(dev); > @@ -949,6 +966,8 @@ static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) > crtc->cursor = cursor_plane; > } > > + vc4_crtc_get_cob_allocation(vc4_crtc); > + > CRTC_WRITE(PV_INTEN, 0); > CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); > ret = devm_request_irq(dev, platform_get_irq(pdev, 0), > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h > index 63cdc28ff7bb..160942a9180e 100644 > --- a/drivers/gpu/drm/vc4/vc4_regs.h > +++ b/drivers/gpu/drm/vc4/vc4_regs.h > @@ -366,7 +366,6 @@ > # define SCALER_DISPBKGND_FILL BIT(24) > > #define SCALER_DISPSTAT0 0x00000048 > -#define SCALER_DISPBASE0 0x0000004c > # define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30) > # define SCALER_DISPSTATX_MODE_SHIFT 30 > # define SCALER_DISPSTATX_MODE_DISABLED 0 > @@ -379,6 +378,20 @@ > # define SCALER_DISPSTATX_FRAME_COUNT_SHIFT 12 > # define SCALER_DISPSTATX_LINE_MASK VC4_MASK(11, 0) > # define SCALER_DISPSTATX_LINE_SHIFT 0 > + > +#define SCALER_DISPBASE0 0x0000004c > +/* Last pixel in the COB (display FIFO memory) allocated to this HVS > + * channel. Must be 4-pixel aligned (and thus 4 pixels less than the > + * next COB base). > + */ > +# define SCALER_DISPBASEX_TOP_MASK VC4_MASK(31, 16) > +# define SCALER_DISPBASEX_TOP_SHIFT 16 > +/* First pixel in the COB (display FIFO memory) allocated to this HVS > + * channel. Must be 4-pixel aligned. > + */ > +# define SCALER_DISPBASEX_BASE_MASK VC4_MASK(15, 0) > +# define SCALER_DISPBASEX_BASE_SHIFT 0 > + > #define SCALER_DISPCTRL1 0x00000050 > #define SCALER_DISPBKGND1 0x00000054 > #define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \ > @@ -389,6 +402,9 @@ > (x) * (SCALER_DISPSTAT1 - \ > SCALER_DISPSTAT0)) > #define SCALER_DISPBASE1 0x0000005c > +#define SCALER_DISPBASEX(x) (SCALER_DISPBASE0 + \ > + (x) * (SCALER_DISPBASE1 - \ > + SCALER_DISPBASE0)) > #define SCALER_DISPCTRL2 0x00000060 > #define SCALER_DISPCTRLX(x) (SCALER_DISPCTRL0 + \ > (x) * (SCALER_DISPCTRL1 - \ >