From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753405AbcGTIhZ (ORCPT ); Wed, 20 Jul 2016 04:37:25 -0400 Received: from mga14.intel.com ([192.55.52.115]:56342 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751873AbcGTIhT (ORCPT ); Wed, 20 Jul 2016 04:37:19 -0400 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.28,393,1464678000"; d="scan'208";a="1025395380" Subject: Re: [PATCH 2/2] x86/insn: perf tools: Add AVX-512 support to the instruction decoder To: Masami Hiramatsu References: <1468932408-9868-1-git-send-email-adrian.hunter@intel.com> <1468932408-9868-3-git-send-email-adrian.hunter@intel.com> <20160720105033.43d4553550031e5dd33d5f9d@kernel.org> Cc: linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Jiri Olsa , Dan Williams , Ingo Molnar , "H. Peter Anvin" , Thomas Gleixner , Andy Lutomirski , X86 ML From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: <578F373C.5000809@intel.com> Date: Wed, 20 Jul 2016 11:33:00 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <20160720105033.43d4553550031e5dd33d5f9d@kernel.org> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 20/07/16 04:50, Masami Hiramatsu wrote: > On Tue, 19 Jul 2016 15:46:48 +0300 > Adrian Hunter wrote: > >> Add support for Intel's AVX-512 instructions to the instruction decoder. >> >> AVX-512 instructions are documented in Intel Architecture Instruction Set >> Extensions Programming Reference (February 2016). >> >> AVX-512 instructions are identifed by a EVEX prefix which, for the purpose >> of instruction decoding, can be treated as though it were a 4-byte VEX >> prefix. >> >> Existing instructions which can now accept an EVEX prefix need not be >> further annotated in the op code map (x86-opcode-map.txt). In the case of >> new instructions, the op code map is updated accordingly. >> >> Also add associated Mask Instructions that are used to manipulate mask >> registers used in AVX-512 instructions. >> >> Add a representative set of instructions to the perf tools new instructons >> test. > > Hmm, could you split this patch into 2 or 3 parts for review? > One is for core-kernel, the others are for perf tools (feature > adding and tests). > > [..] >> diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt >> index 28082de46f0d..92b89fa5f414 100644 >> --- a/arch/x86/lib/x86-opcode-map.txt >> +++ b/arch/x86/lib/x86-opcode-map.txt >> @@ -13,12 +13,17 @@ >> # opcode: escape # escaped-name >> # EndTable >> # >> +# mnemonics that begin with lowercase 'v' accept a VEX or EVEX prefix >> +# mnemonics that begin with lowercase 'k' accept a VEX prefix >> +# > > Ah, nice :) > >> # >> # GrpTable: GrpXXX >> # reg: mnemonic [operand1[,operand2...]] [(extra1)[,(extra2)...] [| 2nd-mnemonic ...] >> # EndTable >> # >> # AVX Superscripts >> +# (ev): this opcode requires EVEX prefix. >> +# (evo): this opcode accepts EVEX prefix. > > Hmm, what the 'o' stands for? I thought it means "EVEX ONLY", but the comment is > opposite. For example, see 'o64', which means "64bit only". > And anyway, as you said above, if all existing instructions can accept EVEX prefix, > why would we need it? > >> -5b: vcvtdq2ps Vps,Wdq | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) >> +5b: vcvtdq2ps Vps,Wdq | vcvtqq2ps Vps,Wqq (evo) | vcvtps2dq Vdq,Wps (66) | vcvttps2dq Vdq,Wps (F3) > > Ah, I see, so that is for the instructions which change the mnemonic since > byte-width is changed... > > OK, so please update the above description of the superscript, like as > "this opcode is changed by EVEX prefix (EVEX opcode)" etc. > > Thank you, > > Thanks for your quick reply. I have updated the patches as you requested and sent V2.