From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ziyuan Xu Date: Thu, 28 Jul 2016 13:54:42 +0800 Subject: [U-Boot] [PATCH] mmc: dw_mmc: fix the wrong Mask bit boundary for fifo_count bit In-Reply-To: <1469683584-21695-1-git-send-email-jh80.chung@samsung.com> References: <1469683584-21695-1-git-send-email-jh80.chung@samsung.com> Message-ID: <57999E22.6030605@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Jaehoon, On 2016?07?28? 13:26, Jaehoon Chung wrote: > According to DesignWare TRM, FIFO_COUNT is bit[29:17]. > If get the correct fifo_count value, it has to use the FIFO_MASK > as 0x1FFF, not 0x1FF. Ah, I have no doubt the fifo_count defined. The fifo depth of Rockchip SoCs is 256, the former work sane coincidentally.:-) Thanks for fix. Reviewed-by: Ziyuan Xu > > Signed-off-by: Jaehoon Chung > --- > include/dwmmc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/include/dwmmc.h b/include/dwmmc.h > index 6aebe96..eb03f7f 100644 > --- a/include/dwmmc.h > +++ b/include/dwmmc.h > @@ -105,7 +105,7 @@ > > /* Status Register */ > #define DWMCI_BUSY (1 << 9) > -#define DWMCI_FIFO_MASK 0x1ff > +#define DWMCI_FIFO_MASK 0x1fff > #define DWMCI_FIFO_SHIFT 17 > > /* FIFOTH Register */