From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Subject: Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq To: Doug Anderson References: <1470143599-8851-1-git-send-email-zhengxing@rock-chips.com> Cc: =?UTF-8?Q?Heiko_St=c3=bcbner?= , "open list:ARM/Rockchip SoC..." , Brian Norris , Tao Huang , zhangqing , Michael Turquette , Stephen Boyd , linux-clk , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" From: Xing Zheng Message-ID: <57A14819.9060309@rock-chips.com> Date: Wed, 3 Aug 2016 09:25:45 +0800 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed List-ID: Hi Doug, On 2016年08月03日 08:49, Doug Anderson wrote: > Xing, > > On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng wrote: >> From: Elaine Zhang >> >> The suggestion that is from IC designer, the correct pll sequence setting >> should be like these: >> ---- >> set pll to slow mode or other plls >> set pll down >> set pll params >> set pll up >> wait pll lock status >> set pll to normal mode >> ---- >> >> Hence, there are potential risks that we need to fix: >> rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock >> rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old params > I still don't understand how that groks with the statement in the TRM: > >> In most cases the PLL programming can be changed on-the-fly and the PLL will simply slew to the new frequency > That makes it sound like these PLLs are super great at dynamic updates. > > Well, I will report it to IC & Doc folkers to update the TRM and make it clear. Thanks. -- - Xing Zheng From mboxrd@z Thu Jan 1 00:00:00 1970 From: Xing Zheng Subject: Re: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq Date: Wed, 3 Aug 2016 09:25:45 +0800 Message-ID: <57A14819.9060309@rock-chips.com> References: <1470143599-8851-1-git-send-email-zhengxing@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Doug Anderson Cc: Tao Huang , zhangqing , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Michael Turquette , Brian Norris , Stephen Boyd , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "open list:ARM/Rockchip SoC..." , linux-clk , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: linux-rockchip.vger.kernel.org SGkgRG91ZywKCk9uIDIwMTblubQwOOaciDAz5pelIDA4OjQ5LCBEb3VnIEFuZGVyc29uIHdyb3Rl Ogo+IFhpbmcsCj4KPiBPbiBUdWUsIEF1ZyAyLCAyMDE2IGF0IDY6MTMgQU0sIFhpbmcgWmhlbmcg PHpoZW5neGluZ0Byb2NrLWNoaXBzLmNvbT4gd3JvdGU6Cj4+IEZyb206IEVsYWluZSBaaGFuZyA8 emhhbmdxaW5nQHJvY2stY2hpcHMuY29tPgo+Pgo+PiBUaGUgc3VnZ2VzdGlvbiB0aGF0IGlzIGZy b20gSUMgZGVzaWduZXIsIHRoZSBjb3JyZWN0IHBsbCBzZXF1ZW5jZSBzZXR0aW5nCj4+IHNob3Vs ZCBiZSBsaWtlIHRoZXNlOgo+PiAtLS0tCj4+ICAgIHNldCBwbGwgdG8gc2xvdyBtb2RlIG9yIG90 aGVyIHBsbHMKPj4gICAgc2V0IHBsbCBkb3duCj4+ICAgIHNldCBwbGwgcGFyYW1zCj4+ICAgIHNl dCBwbGwgdXAKPj4gICAgd2FpdCBwbGwgbG9jayBzdGF0dXMKPj4gICAgc2V0IHBsbCB0byBub3Jt YWwgbW9kZQo+PiAtLS0tCj4+Cj4+IEhlbmNlLCB0aGVyZSBhcmUgcG90ZW50aWFsIHJpc2tzIHRo YXQgd2UgbmVlZCB0byBmaXg6Cj4+IHJvY2tjaGlwX3JrMzM5OV93YWl0X3BsbF9sb2NrIC0gdGlt ZW91dCB3YWl0aW5nIGZvciBwbGwgdG8gbG9jawo+PiByb2NrY2hpcF9yazMzOTlfcGxsX3NldF9w YXJhbXMgLSBwbGwgdXBkYXRlIHVuc3VjZXNzZnVsLCB0cnlpbmcgdG8gcmVzdG9yZSBvbGQgcGFy YW1zCj4gSSBzdGlsbCBkb24ndCB1bmRlcnN0YW5kIGhvdyB0aGF0IGdyb2tzIHdpdGggdGhlIHN0 YXRlbWVudCBpbiB0aGUgVFJNOgo+Cj4+IEluIG1vc3QgY2FzZXMgdGhlIFBMTCBwcm9ncmFtbWlu ZyBjYW4gYmUgY2hhbmdlZCBvbi10aGUtZmx5IGFuZCB0aGUgUExMIHdpbGwgc2ltcGx5IHNsZXcg dG8gdGhlIG5ldyBmcmVxdWVuY3kKPiBUaGF0IG1ha2VzIGl0IHNvdW5kIGxpa2UgdGhlc2UgUExM cyBhcmUgc3VwZXIgZ3JlYXQgYXQgZHluYW1pYyB1cGRhdGVzLgo+Cj4KV2VsbCwgSSB3aWxsIHJl cG9ydCBpdCB0byBJQyAmIERvYyBmb2xrZXJzIHRvIHVwZGF0ZSB0aGUgVFJNIGFuZCBtYWtlIGl0 IApjbGVhci4KClRoYW5rcy4KCi0tIAotIFhpbmcgWmhlbmcKCgoKX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX18KTGludXgtcm9ja2NoaXAgbWFpbGluZyBsaXN0 CkxpbnV4LXJvY2tjaGlwQGxpc3RzLmluZnJhZGVhZC5vcmcKaHR0cDovL2xpc3RzLmluZnJhZGVh ZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1yb2NrY2hpcAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: zhengxing@rock-chips.com (Xing Zheng) Date: Wed, 3 Aug 2016 09:25:45 +0800 Subject: [PATCH] clk: rockchip: rk3399: add pll up and down when change pll freq In-Reply-To: References: <1470143599-8851-1-git-send-email-zhengxing@rock-chips.com> Message-ID: <57A14819.9060309@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Doug, On 2016?08?03? 08:49, Doug Anderson wrote: > Xing, > > On Tue, Aug 2, 2016 at 6:13 AM, Xing Zheng wrote: >> From: Elaine Zhang >> >> The suggestion that is from IC designer, the correct pll sequence setting >> should be like these: >> ---- >> set pll to slow mode or other plls >> set pll down >> set pll params >> set pll up >> wait pll lock status >> set pll to normal mode >> ---- >> >> Hence, there are potential risks that we need to fix: >> rockchip_rk3399_wait_pll_lock - timeout waiting for pll to lock >> rockchip_rk3399_pll_set_params - pll update unsucessful, trying to restore old params > I still don't understand how that groks with the statement in the TRM: > >> In most cases the PLL programming can be changed on-the-fly and the PLL will simply slew to the new frequency > That makes it sound like these PLLs are super great at dynamic updates. > > Well, I will report it to IC & Doc folkers to update the TRM and make it clear. Thanks. -- - Xing Zheng