From mboxrd@z Thu Jan 1 00:00:00 1970 From: Archit Taneja Subject: Re: [PATCH v5 3/4] drm/bridge: analogix_dp: add the PSR function support Date: Wed, 17 Aug 2016 11:11:02 +0530 Message-ID: <57B3F8EE.6030706@codeaurora.org> References: <1469343437-27443-1-git-send-email-ykk@rock-chips.com> <1469343468-27740-1-git-send-email-ykk@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1469343468-27740-1-git-send-email-ykk@rock-chips.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Yakir Yang , Mark Yao , Inki Dae , Thierry Reding , Heiko Stuebner Cc: Krzysztof Kozlowski , linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org, Jingoo Han , emil.l.velikov@gmail.com, dianders@chromium.org, dri-devel@lists.freedesktop.org, Tomasz Figa , Javier Martinez Canillas , daniel.vetter@ffwll.ch, =?UTF-8?Q?St=c3=a9phane_Marchesin?= , Gustavo Padovan , linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGksCgpPbiAwNy8yNC8yMDE2IDEyOjI3IFBNLCBZYWtpciBZYW5nIHdyb3RlOgo+IFRoZSBmdWxs IG5hbWUgb2YgUFNSIGlzIFBhbmVsIFNlbGYgUmVmcmVzaCwgcGFuZWwgZGV2aWNlIGNvdWxkIHJl ZnJlc2gKPiBpdHNlbGYgd2l0aCB0aGUgaGFyZHdhcmUgZnJhbWVidWZmZXIgaW4gcGFuZWwsIHRo aXMgd291bGQgbWFrZSBsb3RzIG9mCj4gc2Vuc2UgdG8gc2F2ZSB0aGUgcG93ZXIgY29uc3VtcHRp b24uCj4KPiBUaGlzIHBhdGNoIGhhdmUgZXhwb3J0ZWQgdHdvIHN5bWJvbHMgZm9yIHBsYXRmb3Jt IGRyaXZlciB0byBpbXBsZW1lbnQKPiB0aGUgUFNSIGZ1bmN0aW9uIGluIGhhcmR3YXJlIHNpZGU6 Cj4gLSBhbmFsb2dpeF9kcF9hY3RpdmVfcHNyKCkKPiAtIGFuYWxvZ2l4X2RwX2luYWN0aXZlX3Bz cigpCgpDb3VsZCB0aGlzIGluIGFueSB3YXkgbWVzcyB0aGluZ3MgdXAgaWYgdGhlIGRldl90eXBl IGlzIEVYWU5PU19EUD8KCk90aGVyd2lzZSwKClJldmlld2VkLWJ5OiBBcmNoaXQgVGFuZWphIDxh cmNoaXR0QGNvZGVhdXJvcmEub3JnPgoKPgo+IFNpZ25lZC1vZmYtYnk6IFlha2lyIFlhbmcgPHlr a0Byb2NrLWNoaXBzLmNvbT4KPiBSZXZpZXdlZC1ieTogU2VhbiBQYXVsIDxzZWFucGF1bEBjaHJv bWl1bS5vcmc+Cj4gLS0tCj4gQ2hhbmdlcyBpbiB2NToKPiAtIEFkZCByZXZpZXdlZCBmbGFnIGZy b20gU2Vhbi4KPgo+IENoYW5nZXMgaW4gdjQuMToKPiAtIFRha2UgdXNlIG9mIGV4aXN0aW5nIGVk cF9wc3JfdnNjIHN0cnVjdCB0byBzd2FwIEhCeCBhbmQgREJ4IHNldHRpbmcuIChTZWFuKQo+IC0g UmVtb3ZlIFBTUl9WSURfQ1JDX0ZMVVNIIHNldHRpbmcgYW5hbG9naXhfZHBfZW5hYmxlX3Bzcl9j cmMoKS4KPiAtIEFkZCBjb21tZW50IGFib3V0IFBCeCBtYWdpYyBudW1iZXJzLiAoU2VhbikKPgo+ IENoYW5nZXMgaW4gdjQ6Cj4gLSBEb3duZ3JhZGUgdGhlIFBTUiB2ZXJzaW9uIHByaW50IG1lc3Nh Z2UgdG8gZGVidWcgbGV2ZWwuIChTZWFuKQo+IC0gUmV0dXJuICd2b2lkJyBpbnN0ZWFkIG9mICdp bnQnIGluIGFuYWxvZ2l4X2RwX2VuYWJsZV9zaW5rX3BzcigpLiAoU2VhbikKPiAtIERlbGV0ZSB0 aGUgdW51c2VkIHJlYWQgZHBjZCBvcGVyYXRpb25zIGluIGFuYWxvZ2l4X2RwX2VuYWJsZV9zaW5r X3BzcigpLiAoU2VhbikKPiAtIERlbGV0ZSB0aGUgYXJiaXRyYXJ5IHVzbGVlcF9yYW5nZSBpbiBh bmFsb2dpeF9kcF9lbmFibGVfcHNyX2NyYy4gKFNlYW4pLgo+IC0gQ2xlYW4gdXAgdGhlIGhhcmRj b2RlZCB2YWx1ZXMgaW4gYW5hbG9naXhfZHBfc2VuZF9wc3Jfc3BkKCkuIChTZWFuKQo+IC0gUmVu YW1lICJhY3RpdmUvaW5hY3RpdmUiIHRvICJlbmFibGUvZGlzYWJsZSIuIChTZWFuLCBEb21pbmlr KQo+IC0gS2VlcCBzZXQgdGhlIFBTUl9WSURfQ1JDX0ZMVVNIIGdhdGUgaW4gYW5hbG9naXhfZHBf ZW5hYmxlX3Bzcl9jcmMoKS4KPgo+IENoYW5nZXMgaW4gdjM6Cj4gLSBzcGxpdCBhbmFsb2dpeF9k cF9lbmFibGVfcHNyKCksIG1ha2UgaXQgbW9yZSBjbGVhcmx5Cj4gICAgICBhbmFsb2dpeF9kcF9k ZXRlY3Rfc2lua19wc3IoKQo+ICAgICAgYW5hbG9naXhfZHBfZW5hYmxlX3NpbmtfcHNyKCkKPiAt IHJlbW92ZSBzb21lIG5vc2llIHJlZ2lzdGVyIHNldHRpbmcgY29tbWVudHMKPgo+IENoYW5nZXMg aW4gdjI6Cj4gLSBpbnRyb2R1Y2UgaW4gdjIsIHNwbGl0ZSB0aGUgY29tbW9uIEFuYWxvZ2l4IERQ IGNoYW5nZXMgb3V0Cj4KPiAgIGRyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9n aXhfZHBfY29yZS5jIHwgODEgKysrKysrKysrKysrKysrKysrKysrKwo+ICAgZHJpdmVycy9ncHUv ZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmggfCAgNSArKwo+ICAgZHJpdmVy cy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9yZWcuYyAgfCA1MSArKysrKysr KysrKysrKwo+ICAgZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9y ZWcuaCAgfCAzNCArKysrKysrKysKPiAgIGluY2x1ZGUvZHJtL2JyaWRnZS9hbmFsb2dpeF9kcC5o ICAgICAgICAgICAgICAgICAgIHwgIDMgKwo+ICAgNSBmaWxlcyBjaGFuZ2VkLCAxNzQgaW5zZXJ0 aW9ucygrKQo+Cj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgv YW5hbG9naXhfZHBfY29yZS5jIGIvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFs b2dpeF9kcF9jb3JlLmMKPiBpbmRleCAzMjcxNWRhLi4zODFiMjVlIDEwMDY0NAo+IC0tLSBhL2Ry aXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfY29yZS5jCj4gKysrIGIv ZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmMKPiBAQCAt OTcsNiArOTcsODMgQEAgc3RhdGljIGludCBhbmFsb2dpeF9kcF9kZXRlY3RfaHBkKHN0cnVjdCBh bmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+ICAgCXJldHVybiAwOwo+ICAgfQo+Cj4gK2ludCBhbmFs b2dpeF9kcF9lbmFibGVfcHNyKHN0cnVjdCBkZXZpY2UgKmRldikKPiArewo+ICsJc3RydWN0IGFu YWxvZ2l4X2RwX2RldmljZSAqZHAgPSBkZXZfZ2V0X2RydmRhdGEoZGV2KTsKPiArCXN0cnVjdCBl ZHBfdnNjX3BzciBwc3JfdnNjOwo+ICsKPiArCWlmICghZHAtPnBzcl9zdXBwb3J0KQo+ICsJCXJl dHVybiAtRUlOVkFMOwo+ICsKPiArCS8qIFByZXBhcmUgVlNDIHBhY2tldCBhcyBwZXIgRURQIDEu NCBzcGVjLCBUYWJsZSA2LjkgKi8KPiArCW1lbXNldCgmcHNyX3ZzYywgMCwgc2l6ZW9mKHBzcl92 c2MpKTsKPiArCXBzcl92c2Muc2RwX2hlYWRlci5IQjAgPSAwOwo+ICsJcHNyX3ZzYy5zZHBfaGVh ZGVyLkhCMSA9IDB4NzsKPiArCXBzcl92c2Muc2RwX2hlYWRlci5IQjIgPSAweDI7Cj4gKwlwc3Jf dnNjLnNkcF9oZWFkZXIuSEIzID0gMHg4Owo+ICsKPiArCXBzcl92c2MuREIwID0gMDsKPiArCXBz cl92c2MuREIxID0gRURQX1ZTQ19QU1JfU1RBVEVfQUNUSVZFIHwgRURQX1ZTQ19QU1JfQ1JDX1ZB TFVFU19WQUxJRDsKPiArCj4gKwlhbmFsb2dpeF9kcF9zZW5kX3Bzcl9zcGQoZHAsICZwc3JfdnNj KTsKPiArCXJldHVybiAwOwo+ICt9Cj4gK0VYUE9SVF9TWU1CT0xfR1BMKGFuYWxvZ2l4X2RwX2Vu YWJsZV9wc3IpOwo+ICsKPiAraW50IGFuYWxvZ2l4X2RwX2Rpc2FibGVfcHNyKHN0cnVjdCBkZXZp Y2UgKmRldikKPiArewo+ICsJc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHAgPSBkZXZfZ2V0 X2RydmRhdGEoZGV2KTsKPiArCXN0cnVjdCBlZHBfdnNjX3BzciBwc3JfdnNjOwo+ICsKPiArCWlm ICghZHAtPnBzcl9zdXBwb3J0KQo+ICsJCXJldHVybiAtRUlOVkFMOwo+ICsKPiArCS8qIFByZXBh cmUgVlNDIHBhY2tldCBhcyBwZXIgRURQIDEuNCBzcGVjLCBUYWJsZSA2LjkgKi8KPiArCW1lbXNl dCgmcHNyX3ZzYywgMCwgc2l6ZW9mKHBzcl92c2MpKTsKPiArCXBzcl92c2Muc2RwX2hlYWRlci5I QjAgPSAwOwo+ICsJcHNyX3ZzYy5zZHBfaGVhZGVyLkhCMSA9IDB4NzsKPiArCXBzcl92c2Muc2Rw X2hlYWRlci5IQjIgPSAweDI7Cj4gKwlwc3JfdnNjLnNkcF9oZWFkZXIuSEIzID0gMHg4Owo+ICsK PiArCXBzcl92c2MuREIwID0gMDsKPiArCXBzcl92c2MuREIxID0gMDsKPiArCj4gKwlhbmFsb2dp eF9kcF9zZW5kX3Bzcl9zcGQoZHAsICZwc3JfdnNjKTsKPiArCXJldHVybiAwOwo+ICt9Cj4gK0VY UE9SVF9TWU1CT0xfR1BMKGFuYWxvZ2l4X2RwX2Rpc2FibGVfcHNyKTsKPiArCj4gK3N0YXRpYyBi b29sIGFuYWxvZ2l4X2RwX2RldGVjdF9zaW5rX3BzcihzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNl ICpkcCkKPiArewo+ICsJdW5zaWduZWQgY2hhciBwc3JfdmVyc2lvbjsKPiArCj4gKwlhbmFsb2dp eF9kcF9yZWFkX2J5dGVfZnJvbV9kcGNkKGRwLCBEUF9QU1JfU1VQUE9SVCwgJnBzcl92ZXJzaW9u KTsKPiArCWRldl9kYmcoZHAtPmRldiwgIlBhbmVsIFBTUiB2ZXJzaW9uIDogJXhcbiIsIHBzcl92 ZXJzaW9uKTsKPiArCj4gKwlyZXR1cm4gKHBzcl92ZXJzaW9uICYgRFBfUFNSX0lTX1NVUFBPUlRF RCkgPyB0cnVlIDogZmFsc2U7Cj4gK30KPiArCj4gK3N0YXRpYyB2b2lkIGFuYWxvZ2l4X2RwX2Vu YWJsZV9zaW5rX3BzcihzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCkKPiArewo+ICsJdW5z aWduZWQgY2hhciBwc3JfZW47Cj4gKwo+ICsJLyogRGlzYWJsZSBwc3IgZnVuY3Rpb24gKi8KPiAr CWFuYWxvZ2l4X2RwX3JlYWRfYnl0ZV9mcm9tX2RwY2QoZHAsIERQX1BTUl9FTl9DRkcsICZwc3Jf ZW4pOwo+ICsJcHNyX2VuICY9IH5EUF9QU1JfRU5BQkxFOwo+ICsJYW5hbG9naXhfZHBfd3JpdGVf Ynl0ZV90b19kcGNkKGRwLCBEUF9QU1JfRU5fQ0ZHLCBwc3JfZW4pOwo+ICsKPiArCS8qIE1haW4t TGluayB0cmFuc21pdHRlciByZW1haW5zIGFjdGl2ZSBkdXJpbmcgUFNSIGFjdGl2ZSBzdGF0ZXMg Ki8KPiArCXBzcl9lbiA9IERQX1BTUl9NQUlOX0xJTktfQUNUSVZFIHwgRFBfUFNSX0NSQ19WRVJJ RklDQVRJT047Cj4gKwlhbmFsb2dpeF9kcF93cml0ZV9ieXRlX3RvX2RwY2QoZHAsIERQX1BTUl9F Tl9DRkcsIHBzcl9lbik7Cj4gKwo+ICsJLyogRW5hYmxlIHBzciBmdW5jdGlvbiAqLwo+ICsJcHNy X2VuID0gRFBfUFNSX0VOQUJMRSB8IERQX1BTUl9NQUlOX0xJTktfQUNUSVZFIHwKPiArCQkgRFBf UFNSX0NSQ19WRVJJRklDQVRJT047Cj4gKwlhbmFsb2dpeF9kcF93cml0ZV9ieXRlX3RvX2RwY2Qo ZHAsIERQX1BTUl9FTl9DRkcsIHBzcl9lbik7Cj4gKwo+ICsJYW5hbG9naXhfZHBfZW5hYmxlX3Bz cl9jcmMoZHApOwo+ICt9Cj4gKwo+ICAgc3RhdGljIHVuc2lnbmVkIGNoYXIgYW5hbG9naXhfZHBf Y2FsY19lZGlkX2NoZWNrX3N1bSh1bnNpZ25lZCBjaGFyICplZGlkX2RhdGEpCj4gICB7Cj4gICAJ aW50IGk7Cj4gQEAgLTkyMSw2ICs5OTgsMTAgQEAgc3RhdGljIHZvaWQgYW5hbG9naXhfZHBfY29t bWl0KHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKQo+Cj4gICAJLyogRW5hYmxlIHZpZGVv ICovCj4gICAJYW5hbG9naXhfZHBfc3RhcnRfdmlkZW8oZHApOwo+ICsKPiArCWRwLT5wc3Jfc3Vw cG9ydCA9IGFuYWxvZ2l4X2RwX2RldGVjdF9zaW5rX3BzcihkcCk7Cj4gKwlpZiAoZHAtPnBzcl9z dXBwb3J0KQo+ICsJCWFuYWxvZ2l4X2RwX2VuYWJsZV9zaW5rX3BzcihkcCk7Cj4gICB9Cj4KPiAg IGludCBhbmFsb2dpeF9kcF9nZXRfbW9kZXMoc3RydWN0IGRybV9jb25uZWN0b3IgKmNvbm5lY3Rv cikKPiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dp eF9kcF9jb3JlLmggYi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2Rw X2NvcmUuaAo+IGluZGV4IGI0NTYzODAuLjE3ZmJjZWUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9n cHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9jb3JlLmgKPiArKysgYi9kcml2ZXJz L2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX2NvcmUuaAo+IEBAIC0xNzcsNiAr MTc3LDcgQEAgc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSB7Cj4gICAJaW50CQkJaHBkX2dwaW87 Cj4gICAJYm9vbCAgICAgICAgICAgICAgICAgICAgZm9yY2VfaHBkOwo+ICAgCXVuc2lnbmVkIGNo YXIgICAgICAgICAgIGVkaWRbRURJRF9CTE9DS19MRU5HVEggKiAyXTsKPiArCWJvb2wJCQlwc3Jf c3VwcG9ydDsKPgo+ICAgCXN0cnVjdCBhbmFsb2dpeF9kcF9wbGF0X2RhdGEgKnBsYXRfZGF0YTsK PiAgIH07Cj4gQEAgLTI3OCw0ICsyNzksOCBAQCBpbnQgYW5hbG9naXhfZHBfaXNfdmlkZW9fc3Ry ZWFtX29uKHN0cnVjdCBhbmFsb2dpeF9kcF9kZXZpY2UgKmRwKTsKPiAgIHZvaWQgYW5hbG9naXhf ZHBfY29uZmlnX3ZpZGVvX3NsYXZlX21vZGUoc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHAp Owo+ICAgdm9pZCBhbmFsb2dpeF9kcF9lbmFibGVfc2NyYW1ibGluZyhzdHJ1Y3QgYW5hbG9naXhf ZHBfZGV2aWNlICpkcCk7Cj4gICB2b2lkIGFuYWxvZ2l4X2RwX2Rpc2FibGVfc2NyYW1ibGluZyhz dHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCk7Cj4gK3ZvaWQgYW5hbG9naXhfZHBfZW5hYmxl X3Bzcl9jcmMoc3RydWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApOwo+ICt2b2lkIGFuYWxvZ2l4 X2RwX3NlbmRfcHNyX3NwZChzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpkcCwKPiArCQkJICAg ICAgc3RydWN0IGVkcF92c2NfcHNyICp2c2MpOwo+ICsKPiAgICNlbmRpZiAvKiBfQU5BTE9HSVhf RFBfQ09SRV9IICovCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9n aXgvYW5hbG9naXhfZHBfcmVnLmMgYi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2Fu YWxvZ2l4X2RwX3JlZy5jCj4gaW5kZXggNDgwMzBmMC4uNTJjMWI2YiAxMDA2NDQKPiAtLS0gYS9k cml2ZXJzL2dwdS9kcm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX3JlZy5jCj4gKysrIGIv ZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9kcF9yZWcuYwo+IEBAIC0x MzIyLDMgKzEzMjIsNTQgQEAgdm9pZCBhbmFsb2dpeF9kcF9kaXNhYmxlX3NjcmFtYmxpbmcoc3Ry dWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApCj4gICAJcmVnIHw9IFNDUkFNQkxJTkdfRElTQUJM RTsKPiAgIAl3cml0ZWwocmVnLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9UUkFJTklOR19Q VE5fU0VUKTsKPiAgIH0KPiArCj4gK3ZvaWQgYW5hbG9naXhfZHBfZW5hYmxlX3Bzcl9jcmMoc3Ry dWN0IGFuYWxvZ2l4X2RwX2RldmljZSAqZHApCj4gK3sKPiArCXdyaXRlbChQU1JfVklEX0NSQ19F TkFCTEUsIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX0NSQ19DT04pOwo+ICt9Cj4gKwo+ICt2 b2lkIGFuYWxvZ2l4X2RwX3NlbmRfcHNyX3NwZChzdHJ1Y3QgYW5hbG9naXhfZHBfZGV2aWNlICpk cCwKPiArCQkJICAgICAgc3RydWN0IGVkcF92c2NfcHNyICp2c2MpCj4gK3sKPiArCXVuc2lnbmVk IGludCB2YWw7Cj4gKwo+ICsJLyogZG9uJ3Qgc2VuZCBpbmZvIGZyYW1lICovCj4gKwl2YWwgPSBy ZWFkbChkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9QS1RfU0VORF9DVEwpOwo+ICsJdmFsICY9 IH5JRl9FTjsKPiArCXdyaXRlbCh2YWwsIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1BLVF9T RU5EX0NUTCk7Cj4gKwo+ICsJLyogY29uZmlndXJlIHNpbmdsZSBmcmFtZSB1cGRhdGUgbW9kZSAq Lwo+ICsJd3JpdGVsKFBTUl9GUkFNRV9VUF9UWVBFX0JVUlNUIHwgUFNSX0NSQ19TRUxfSEFSRFdB UkUsCj4gKwkgICAgICAgZHAtPnJlZ19iYXNlICsgQU5BTE9HSVhfRFBfUFNSX0ZSQU1FX1VQREFU RV9DVFJMKTsKPiArCj4gKwkvKiBjb25maWd1cmUgVlNDIEhCMH5IQjMgKi8KPiArCXdyaXRlbCh2 c2MtPnNkcF9oZWFkZXIuSEIwLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfSEIwKTsK PiArCXdyaXRlbCh2c2MtPnNkcF9oZWFkZXIuSEIxLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9E UF9TUERfSEIxKTsKPiArCXdyaXRlbCh2c2MtPnNkcF9oZWFkZXIuSEIyLCBkcC0+cmVnX2Jhc2Ug KyBBTkFMT0dJWF9EUF9TUERfSEIyKTsKPiArCXdyaXRlbCh2c2MtPnNkcF9oZWFkZXIuSEIzLCBk cC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfSEIzKTsKPiArCj4gKwkvKiBjb25maWd1cmUg cmV1c2VkIFZTQyBQQjB+UEIzLCBtYWdpYyBudW1iZXIgZnJvbSB2ZW5kb3IgKi8KPiArCXdyaXRl bCgweDAwLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfUEIwKTsKPiArCXdyaXRlbCgw eDE2LCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfUEIxKTsKPiArCXdyaXRlbCgweENF LCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfUEIyKTsKPiArCXdyaXRlbCgweDVELCBk cC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9TUERfUEIzKTsKPiArCj4gKwkvKiBjb25maWd1cmUg REIwIC8gREIxIHZhbHVlcyAqLwo+ICsJd3JpdGVsKHZzYy0+REIwLCBkcC0+cmVnX2Jhc2UgKyBB TkFMT0dJWF9EUF9WU0NfU0hBRE9XX0RCMCk7Cj4gKwl3cml0ZWwodnNjLT5EQjEsIGRwLT5yZWdf YmFzZSArIEFOQUxPR0lYX0RQX1ZTQ19TSEFET1dfREIxKTsKPiArCj4gKwkvKiBzZXQgcmV1c2Ug c3BkIGluZm9yZnJhbWUgKi8KPiArCXZhbCA9IHJlYWRsKGRwLT5yZWdfYmFzZSArIEFOQUxPR0lY X0RQX1ZJREVPX0NUTF8zKTsKPiArCXZhbCB8PSBSRVVTRV9TUERfRU47Cj4gKwl3cml0ZWwodmFs LCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9WSURFT19DVExfMyk7Cj4gKwo+ICsJLyogbWFy ayBpbmZvIGZyYW1lIHVwZGF0ZSAqLwo+ICsJdmFsID0gcmVhZGwoZHAtPnJlZ19iYXNlICsgQU5B TE9HSVhfRFBfUEtUX1NFTkRfQ1RMKTsKPiArCXZhbCA9ICh2YWwgfCBJRl9VUCkgJiB+SUZfRU47 Cj4gKwl3cml0ZWwodmFsLCBkcC0+cmVnX2Jhc2UgKyBBTkFMT0dJWF9EUF9QS1RfU0VORF9DVEwp Owo+ICsKPiArCS8qIHNlbmQgaW5mbyBmcmFtZSAqLwo+ICsJdmFsID0gcmVhZGwoZHAtPnJlZ19i YXNlICsgQU5BTE9HSVhfRFBfUEtUX1NFTkRfQ1RMKTsKPiArCXZhbCB8PSBJRl9FTjsKPiArCXdy aXRlbCh2YWwsIGRwLT5yZWdfYmFzZSArIEFOQUxPR0lYX0RQX1BLVF9TRU5EX0NUTCk7Cj4gK30K PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hbmFsb2dpeC9hbmFsb2dpeF9k cF9yZWcuaCBiL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfcmVn LmgKPiBpbmRleCBjZGNjNmM1Li40MDIwMGM2IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2Ry bS9icmlkZ2UvYW5hbG9naXgvYW5hbG9naXhfZHBfcmVnLmgKPiArKysgYi9kcml2ZXJzL2dwdS9k cm0vYnJpZGdlL2FuYWxvZ2l4L2FuYWxvZ2l4X2RwX3JlZy5oCj4gQEAgLTIyLDYgKzIyLDggQEAK PiAgICNkZWZpbmUgQU5BTE9HSVhfRFBfVklERU9fQ1RMXzgJCQkweDNDCj4gICAjZGVmaW5lIEFO QUxPR0lYX0RQX1ZJREVPX0NUTF8xMAkJMHg0NAo+Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BE SUZfQVVESU9fQ1RMXzAJCTB4RDgKPiArCj4gICAjZGVmaW5lIEFOQUxPR0lYX0RQX1BMTF9SRUdf MQkJCTB4ZmMKPiAgICNkZWZpbmUgQU5BTE9HSVhfRFBfUExMX1JFR18yCQkJMHg5ZTQKPiAgICNk ZWZpbmUgQU5BTE9HSVhfRFBfUExMX1JFR18zCQkJMHg5ZTgKPiBAQCAtMzAsNiArMzIsMjEgQEAK Pgo+ICAgI2RlZmluZSBBTkFMT0dJWF9EUF9QRAkJCQkweDEyYwo+Cj4gKyNkZWZpbmUgQU5BTE9H SVhfRFBfSUZfVFlQRQkJCTB4MjQ0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfSUZfUEtUX0RCMQkJ CTB4MjU0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfSUZfUEtUX0RCMgkJCTB4MjU4Cj4gKyNkZWZp bmUgQU5BTE9HSVhfRFBfU1BEX0hCMAkJCTB4MkY4Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BE X0hCMQkJCTB4MkZDCj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BEX0hCMgkJCTB4MzAwCj4gKyNk ZWZpbmUgQU5BTE9HSVhfRFBfU1BEX0hCMwkJCTB4MzA0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBf U1BEX1BCMAkJCTB4MzA4Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BEX1BCMQkJCTB4MzBDCj4g KyNkZWZpbmUgQU5BTE9HSVhfRFBfU1BEX1BCMgkJCTB4MzEwCj4gKyNkZWZpbmUgQU5BTE9HSVhf RFBfU1BEX1BCMwkJCTB4MzE0Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfUFNSX0ZSQU1FX1VQREFU RV9DVFJMCTB4MzE4Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfVlNDX1NIQURPV19EQjAJCTB4MzFD Cj4gKyNkZWZpbmUgQU5BTE9HSVhfRFBfVlNDX1NIQURPV19EQjEJCTB4MzIwCj4gKwo+ICAgI2Rl ZmluZSBBTkFMT0dJWF9EUF9MQU5FX01BUAkJCTB4MzVDCj4KPiAgICNkZWZpbmUgQU5BTE9HSVhf RFBfQU5BTE9HX0NUTF8xCQkweDM3MAo+IEBAIC0xMDMsNiArMTIwLDggQEAKPgo+ICAgI2RlZmlu ZSBBTkFMT0dJWF9EUF9TT0NfR0VORVJBTF9DVEwJCTB4ODAwCj4KPiArI2RlZmluZSBBTkFMT0dJ WF9EUF9DUkNfQ09OCQkJMHg4OTAKPiArCj4gICAvKiBBTkFMT0dJWF9EUF9UWF9TV19SRVNFVCAq Lwo+ICAgI2RlZmluZSBSRVNFVF9EUF9UWAkJCQkoMHgxIDw8IDApCj4KPiBAQCAtMTUxLDYgKzE3 MCw3IEBACj4gICAjZGVmaW5lIFZJRF9DSEtfVVBEQVRFX1RZUEVfU0hJRlQJCSg0KQo+ICAgI2Rl ZmluZSBWSURfQ0hLX1VQREFURV9UWVBFXzEJCQkoMHgxIDw8IDQpCj4gICAjZGVmaW5lIFZJRF9D SEtfVVBEQVRFX1RZUEVfMAkJCSgweDAgPDwgNCkKPiArI2RlZmluZSBSRVVTRV9TUERfRU4JCQkJ KDB4MSA8PCAzKQo+Cj4gICAvKiBBTkFMT0dJWF9EUF9WSURFT19DVExfOCAqLwo+ICAgI2RlZmlu ZSBWSURfSFJFU19USCh4KQkJCQkoKCh4KSAmIDB4ZikgPDwgNCkKPiBAQCAtMTY3LDYgKzE4Nywx MiBAQAo+ICAgI2RlZmluZSBSRUZfQ0xLXzI3TQkJCQkoMHgwIDw8IDApCj4gICAjZGVmaW5lIFJF Rl9DTEtfTUFTSwkJCQkoMHgxIDw8IDApCj4KPiArLyogQU5BTE9HSVhfRFBfUFNSX0ZSQU1FX1VQ REFURV9DVFJMICovCj4gKyNkZWZpbmUgUFNSX0ZSQU1FX1VQX1RZUEVfQlVSU1QJCQkoMHgxIDw8 IDApCj4gKyNkZWZpbmUgUFNSX0ZSQU1FX1VQX1RZUEVfU0lOR0xFCQkoMHgwIDw8IDApCj4gKyNk ZWZpbmUgUFNSX0NSQ19TRUxfSEFSRFdBUkUJCQkoMHgxIDw8IDEpCj4gKyNkZWZpbmUgUFNSX0NS Q19TRUxfTUFOVUFMTFkJCQkoMHgwIDw8IDEpCj4gKwo+ICAgLyogQU5BTE9HSVhfRFBfTEFORV9N QVAgKi8KPiAgICNkZWZpbmUgTEFORTNfTUFQX0xPR0lDX0xBTkVfMAkJCSgweDAgPDwgNikKPiAg ICNkZWZpbmUgTEFORTNfTUFQX0xPR0lDX0xBTkVfMQkJCSgweDEgPDwgNikKPiBAQCAtMzc2LDQg KzQwMiwxMiBAQAo+ICAgI2RlZmluZSBWSURFT19NT0RFX1NMQVZFX01PREUJCQkoMHgxIDw8IDAp Cj4gICAjZGVmaW5lIFZJREVPX01PREVfTUFTVEVSX01PREUJCQkoMHgwIDw8IDApCj4KPiArLyog QU5BTE9HSVhfRFBfUEtUX1NFTkRfQ1RMICovCj4gKyNkZWZpbmUgSUZfVVAJCQkJCSgweDEgPDwg NCkKPiArI2RlZmluZSBJRl9FTgkJCQkJKDB4MSA8PCAwKQo+ICsKPiArLyogQU5BTE9HSVhfRFBf Q1JDX0NPTiAqLwo+ICsjZGVmaW5lIFBTUl9WSURfQ1JDX0ZMVVNICQkJKDB4MSA8PCAyKQo+ICsj ZGVmaW5lIFBTUl9WSURfQ1JDX0VOQUJMRQkJCSgweDEgPDwgMCkKPiArCj4gICAjZW5kaWYgLyog X0FOQUxPR0lYX0RQX1JFR19IICovCj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvZHJtL2JyaWRnZS9h bmFsb2dpeF9kcC5oIGIvaW5jbHVkZS9kcm0vYnJpZGdlL2FuYWxvZ2l4X2RwLmgKPiBpbmRleCAy NjFiODZkLi45Y2Q4ODM4IDEwMDY0NAo+IC0tLSBhL2luY2x1ZGUvZHJtL2JyaWRnZS9hbmFsb2dp eF9kcC5oCj4gKysrIGIvaW5jbHVkZS9kcm0vYnJpZGdlL2FuYWxvZ2l4X2RwLmgKPiBAQCAtMzgs NiArMzgsOSBAQCBzdHJ1Y3QgYW5hbG9naXhfZHBfcGxhdF9kYXRhIHsKPiAgIAkJCSBzdHJ1Y3Qg ZHJtX2Nvbm5lY3RvciAqKTsKPiAgIH07Cj4KPiAraW50IGFuYWxvZ2l4X2RwX2VuYWJsZV9wc3Io c3RydWN0IGRldmljZSAqZGV2KTsKPiAraW50IGFuYWxvZ2l4X2RwX2Rpc2FibGVfcHNyKHN0cnVj dCBkZXZpY2UgKmRldik7Cj4gKwo+ICAgaW50IGFuYWxvZ2l4X2RwX3Jlc3VtZShzdHJ1Y3QgZGV2 aWNlICpkZXYpOwo+ICAgaW50IGFuYWxvZ2l4X2RwX3N1c3BlbmQoc3RydWN0IGRldmljZSAqZGV2 KTsKPgo+CgotLSAKUXVhbGNvbW0gSW5ub3ZhdGlvbiBDZW50ZXIsIEluYy4gaXMgYSBtZW1iZXIg b2YgQ29kZSBBdXJvcmEgRm9ydW0sCmEgTGludXggRm91bmRhdGlvbiBDb2xsYWJvcmF0aXZlIFBy b2plY3QKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753639AbcHQFmQ (ORCPT ); Wed, 17 Aug 2016 01:42:16 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:55354 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750903AbcHQFmO (ORCPT ); Wed, 17 Aug 2016 01:42:14 -0400 Subject: Re: [PATCH v5 3/4] drm/bridge: analogix_dp: add the PSR function support To: Yakir Yang , Mark Yao , Inki Dae , Thierry Reding , Heiko Stuebner References: <1469343437-27443-1-git-send-email-ykk@rock-chips.com> <1469343468-27740-1-git-send-email-ykk@rock-chips.com> Cc: Jingoo Han , Javier Martinez Canillas , =?UTF-8?Q?St=c3=a9phane_Marchesin?= , Sean Paul , Tomasz Figa , dianders@chromium.org, David Airlie , daniel.vetter@ffwll.ch, Krzysztof Kozlowski , emil.l.velikov@gmail.com, Gustavo Padovan , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org, linux-rockchip@lists.infradead.org From: Archit Taneja Message-ID: <57B3F8EE.6030706@codeaurora.org> Date: Wed, 17 Aug 2016 11:11:02 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1469343468-27740-1-git-send-email-ykk@rock-chips.com> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 07/24/2016 12:27 PM, Yakir Yang wrote: > The full name of PSR is Panel Self Refresh, panel device could refresh > itself with the hardware framebuffer in panel, this would make lots of > sense to save the power consumption. > > This patch have exported two symbols for platform driver to implement > the PSR function in hardware side: > - analogix_dp_active_psr() > - analogix_dp_inactive_psr() Could this in any way mess things up if the dev_type is EXYNOS_DP? Otherwise, Reviewed-by: Archit Taneja > > Signed-off-by: Yakir Yang > Reviewed-by: Sean Paul > --- > Changes in v5: > - Add reviewed flag from Sean. > > Changes in v4.1: > - Take use of existing edp_psr_vsc struct to swap HBx and DBx setting. (Sean) > - Remove PSR_VID_CRC_FLUSH setting analogix_dp_enable_psr_crc(). > - Add comment about PBx magic numbers. (Sean) > > Changes in v4: > - Downgrade the PSR version print message to debug level. (Sean) > - Return 'void' instead of 'int' in analogix_dp_enable_sink_psr(). (Sean) > - Delete the unused read dpcd operations in analogix_dp_enable_sink_psr(). (Sean) > - Delete the arbitrary usleep_range in analogix_dp_enable_psr_crc. (Sean). > - Clean up the hardcoded values in analogix_dp_send_psr_spd(). (Sean) > - Rename "active/inactive" to "enable/disable". (Sean, Dominik) > - Keep set the PSR_VID_CRC_FLUSH gate in analogix_dp_enable_psr_crc(). > > Changes in v3: > - split analogix_dp_enable_psr(), make it more clearly > analogix_dp_detect_sink_psr() > analogix_dp_enable_sink_psr() > - remove some nosie register setting comments > > Changes in v2: > - introduce in v2, splite the common Analogix DP changes out > > drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 81 ++++++++++++++++++++++ > drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 ++ > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 51 ++++++++++++++ > drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 34 +++++++++ > include/drm/bridge/analogix_dp.h | 3 + > 5 files changed, 174 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > index 32715da..381b25e 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c > @@ -97,6 +97,83 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp) > return 0; > } > > +int analogix_dp_enable_psr(struct device *dev) > +{ > + struct analogix_dp_device *dp = dev_get_drvdata(dev); > + struct edp_vsc_psr psr_vsc; > + > + if (!dp->psr_support) > + return -EINVAL; > + > + /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ > + memset(&psr_vsc, 0, sizeof(psr_vsc)); > + psr_vsc.sdp_header.HB0 = 0; > + psr_vsc.sdp_header.HB1 = 0x7; > + psr_vsc.sdp_header.HB2 = 0x2; > + psr_vsc.sdp_header.HB3 = 0x8; > + > + psr_vsc.DB0 = 0; > + psr_vsc.DB1 = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID; > + > + analogix_dp_send_psr_spd(dp, &psr_vsc); > + return 0; > +} > +EXPORT_SYMBOL_GPL(analogix_dp_enable_psr); > + > +int analogix_dp_disable_psr(struct device *dev) > +{ > + struct analogix_dp_device *dp = dev_get_drvdata(dev); > + struct edp_vsc_psr psr_vsc; > + > + if (!dp->psr_support) > + return -EINVAL; > + > + /* Prepare VSC packet as per EDP 1.4 spec, Table 6.9 */ > + memset(&psr_vsc, 0, sizeof(psr_vsc)); > + psr_vsc.sdp_header.HB0 = 0; > + psr_vsc.sdp_header.HB1 = 0x7; > + psr_vsc.sdp_header.HB2 = 0x2; > + psr_vsc.sdp_header.HB3 = 0x8; > + > + psr_vsc.DB0 = 0; > + psr_vsc.DB1 = 0; > + > + analogix_dp_send_psr_spd(dp, &psr_vsc); > + return 0; > +} > +EXPORT_SYMBOL_GPL(analogix_dp_disable_psr); > + > +static bool analogix_dp_detect_sink_psr(struct analogix_dp_device *dp) > +{ > + unsigned char psr_version; > + > + analogix_dp_read_byte_from_dpcd(dp, DP_PSR_SUPPORT, &psr_version); > + dev_dbg(dp->dev, "Panel PSR version : %x\n", psr_version); > + > + return (psr_version & DP_PSR_IS_SUPPORTED) ? true : false; > +} > + > +static void analogix_dp_enable_sink_psr(struct analogix_dp_device *dp) > +{ > + unsigned char psr_en; > + > + /* Disable psr function */ > + analogix_dp_read_byte_from_dpcd(dp, DP_PSR_EN_CFG, &psr_en); > + psr_en &= ~DP_PSR_ENABLE; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + /* Main-Link transmitter remains active during PSR active states */ > + psr_en = DP_PSR_MAIN_LINK_ACTIVE | DP_PSR_CRC_VERIFICATION; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + /* Enable psr function */ > + psr_en = DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE | > + DP_PSR_CRC_VERIFICATION; > + analogix_dp_write_byte_to_dpcd(dp, DP_PSR_EN_CFG, psr_en); > + > + analogix_dp_enable_psr_crc(dp); > +} > + > static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data) > { > int i; > @@ -921,6 +998,10 @@ static void analogix_dp_commit(struct analogix_dp_device *dp) > > /* Enable video */ > analogix_dp_start_video(dp); > + > + dp->psr_support = analogix_dp_detect_sink_psr(dp); > + if (dp->psr_support) > + analogix_dp_enable_sink_psr(dp); > } > > int analogix_dp_get_modes(struct drm_connector *connector) > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > index b456380..17fbcee 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h > @@ -177,6 +177,7 @@ struct analogix_dp_device { > int hpd_gpio; > bool force_hpd; > unsigned char edid[EDID_BLOCK_LENGTH * 2]; > + bool psr_support; > > struct analogix_dp_plat_data *plat_data; > }; > @@ -278,4 +279,8 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp); > void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp); > void analogix_dp_enable_scrambling(struct analogix_dp_device *dp); > void analogix_dp_disable_scrambling(struct analogix_dp_device *dp); > +void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp); > +void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, > + struct edp_vsc_psr *vsc); > + > #endif /* _ANALOGIX_DP_CORE_H */ > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > index 48030f0..52c1b6b 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c > @@ -1322,3 +1322,54 @@ void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) > reg |= SCRAMBLING_DISABLE; > writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); > } > + > +void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp) > +{ > + writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON); > +} > + > +void analogix_dp_send_psr_spd(struct analogix_dp_device *dp, > + struct edp_vsc_psr *vsc) > +{ > + unsigned int val; > + > + /* don't send info frame */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val &= ~IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + > + /* configure single frame update mode */ > + writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE, > + dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); > + > + /* configure VSC HB0~HB3 */ > + writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); > + writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); > + writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); > + writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); > + > + /* configure reused VSC PB0~PB3, magic number from vendor */ > + writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0); > + writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1); > + writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2); > + writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3); > + > + /* configure DB0 / DB1 values */ > + writel(vsc->DB0, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); > + writel(vsc->DB1, dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); > + > + /* set reuse spd inforframe */ > + val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); > + val |= REUSE_SPD_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); > + > + /* mark info frame update */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val = (val | IF_UP) & ~IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + > + /* send info frame */ > + val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > + val |= IF_EN; > + writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); > +} > diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > index cdcc6c5..40200c6 100644 > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h > @@ -22,6 +22,8 @@ > #define ANALOGIX_DP_VIDEO_CTL_8 0x3C > #define ANALOGIX_DP_VIDEO_CTL_10 0x44 > > +#define ANALOGIX_DP_SPDIF_AUDIO_CTL_0 0xD8 > + > #define ANALOGIX_DP_PLL_REG_1 0xfc > #define ANALOGIX_DP_PLL_REG_2 0x9e4 > #define ANALOGIX_DP_PLL_REG_3 0x9e8 > @@ -30,6 +32,21 @@ > > #define ANALOGIX_DP_PD 0x12c > > +#define ANALOGIX_DP_IF_TYPE 0x244 > +#define ANALOGIX_DP_IF_PKT_DB1 0x254 > +#define ANALOGIX_DP_IF_PKT_DB2 0x258 > +#define ANALOGIX_DP_SPD_HB0 0x2F8 > +#define ANALOGIX_DP_SPD_HB1 0x2FC > +#define ANALOGIX_DP_SPD_HB2 0x300 > +#define ANALOGIX_DP_SPD_HB3 0x304 > +#define ANALOGIX_DP_SPD_PB0 0x308 > +#define ANALOGIX_DP_SPD_PB1 0x30C > +#define ANALOGIX_DP_SPD_PB2 0x310 > +#define ANALOGIX_DP_SPD_PB3 0x314 > +#define ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL 0x318 > +#define ANALOGIX_DP_VSC_SHADOW_DB0 0x31C > +#define ANALOGIX_DP_VSC_SHADOW_DB1 0x320 > + > #define ANALOGIX_DP_LANE_MAP 0x35C > > #define ANALOGIX_DP_ANALOG_CTL_1 0x370 > @@ -103,6 +120,8 @@ > > #define ANALOGIX_DP_SOC_GENERAL_CTL 0x800 > > +#define ANALOGIX_DP_CRC_CON 0x890 > + > /* ANALOGIX_DP_TX_SW_RESET */ > #define RESET_DP_TX (0x1 << 0) > > @@ -151,6 +170,7 @@ > #define VID_CHK_UPDATE_TYPE_SHIFT (4) > #define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) > #define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) > +#define REUSE_SPD_EN (0x1 << 3) > > /* ANALOGIX_DP_VIDEO_CTL_8 */ > #define VID_HRES_TH(x) (((x) & 0xf) << 4) > @@ -167,6 +187,12 @@ > #define REF_CLK_27M (0x0 << 0) > #define REF_CLK_MASK (0x1 << 0) > > +/* ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL */ > +#define PSR_FRAME_UP_TYPE_BURST (0x1 << 0) > +#define PSR_FRAME_UP_TYPE_SINGLE (0x0 << 0) > +#define PSR_CRC_SEL_HARDWARE (0x1 << 1) > +#define PSR_CRC_SEL_MANUALLY (0x0 << 1) > + > /* ANALOGIX_DP_LANE_MAP */ > #define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6) > #define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6) > @@ -376,4 +402,12 @@ > #define VIDEO_MODE_SLAVE_MODE (0x1 << 0) > #define VIDEO_MODE_MASTER_MODE (0x0 << 0) > > +/* ANALOGIX_DP_PKT_SEND_CTL */ > +#define IF_UP (0x1 << 4) > +#define IF_EN (0x1 << 0) > + > +/* ANALOGIX_DP_CRC_CON */ > +#define PSR_VID_CRC_FLUSH (0x1 << 2) > +#define PSR_VID_CRC_ENABLE (0x1 << 0) > + > #endif /* _ANALOGIX_DP_REG_H */ > diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h > index 261b86d..9cd8838 100644 > --- a/include/drm/bridge/analogix_dp.h > +++ b/include/drm/bridge/analogix_dp.h > @@ -38,6 +38,9 @@ struct analogix_dp_plat_data { > struct drm_connector *); > }; > > +int analogix_dp_enable_psr(struct device *dev); > +int analogix_dp_disable_psr(struct device *dev); > + > int analogix_dp_resume(struct device *dev); > int analogix_dp_suspend(struct device *dev); > > -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project