From mboxrd@z Thu Jan 1 00:00:00 1970 From: Mark yao Subject: Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number Date: Thu, 18 Aug 2016 17:08:14 +0800 Message-ID: <57B57AFE.2030706@rock-chips.com> References: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Sean Paul , tfiga@chromium.org, dri-devel@lists.freedesktop.org Cc: linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org List-Id: linux-rockchip.vger.kernel.org SGkgU2VhbgoKVGhhbmtzIGZvciBzZW5kIHYzIHBhdGNoIGZvciByazMzOTkgdm9wIHN1cHBvcnQu CgpCdXQgc29ycnkgZm9yIHRoYXQsIEkgaGFkIGNoYW5nZWQgbXkgbWluZCwgdGhvc2UgcGF0Y2hl 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RFVMRV9ERVZJQ0VfVEFCTEUob2YsIHZvcF9kcml2ZXJfZHRfbWF0Y2gpOwoKCi0tIArvvK1hcmsg WWFvCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: mark.yao@rock-chips.com (Mark yao) Date: Thu, 18 Aug 2016 17:08:14 +0800 Subject: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number In-Reply-To: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> References: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> Message-ID: <57B57AFE.2030706@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016?08?18? 01:20, Sean Paul wrote: > From: Mark Yao > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- ?ark Yao From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753665AbcHRJIY (ORCPT ); Thu, 18 Aug 2016 05:08:24 -0400 Received: from regular1.263xmail.com ([211.150.99.140]:58094 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752864AbcHRJIW (ORCPT ); Thu, 18 Aug 2016 05:08:22 -0400 X-263anti-spam: KSV:0;BIG:0;ABS:1;DNS:0;ATT:0;SPF:S; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 1 X-SKE-CHECKED: 1 X-ADDR-CHECKED: 0 X-RL-SENDER: mark.yao@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: mark.yao@rock-chips.com X-UNIQUE-TAG: <315c250f207cd0035c3056689b8ebe86> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v3 1/5] drm/rockchip: sort registers define by chip's number To: Sean Paul , tfiga@chromium.org, dri-devel@lists.freedesktop.org References: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> Cc: linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, heiko@sntech.de From: Mark yao Message-ID: <57B57AFE.2030706@rock-chips.com> Date: Thu, 18 Aug 2016 17:08:14 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <1471454452-2151-1-git-send-email-seanpaul@chromium.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sean Thanks for send v3 patch for rk3399 vop support. But sorry for that, I had changed my mind, those patches are deprecated, I have new rk3399 patch on my downstream kernel, I will upstream soon. Thanks. On 2016年08月18日 01:20, Sean Paul wrote: > From: Mark Yao > > No functional changes, sort the vop registers to make > code more readable. > > Signed-off-by: Mark Yao > [seanpaul resolved conflict with name change from _3066 to _3036] > Signed-off-by: Sean Paul > --- > > Changes in v3: > - Fix typo from _3066 _3036 (Tomasz Figa) > > drivers/gpu/drm/rockchip/rockchip_vop_reg.c | 168 ++++++++++++++-------------- > 1 file changed, 84 insertions(+), 84 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > index 919992c..44caf14 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > +++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c > @@ -50,6 +50,88 @@ static const uint32_t formats_win_lite[] = { > DRM_FORMAT_BGR565, > }; > > +static const struct vop_scl_regs rk3036_win_scl = { > + .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > + .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > + .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > + .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win0_data = { > + .scl = &rk3036_win_scl, > + .data_formats = formats_win_full, > + .nformats = ARRAY_SIZE(formats_win_full), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > + .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > + .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > + .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > +}; > + > +static const struct vop_win_phy rk3036_win1_data = { > + .data_formats = formats_win_lite, > + .nformats = ARRAY_SIZE(formats_win_lite), > + .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > + .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > + .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > + .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > + .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > + .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > + .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > + .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > +}; > + > +static const struct vop_win_data rk3036_vop_win_data[] = { > + { .base = 0x00, .phy = &rk3036_win0_data, > + .type = DRM_PLANE_TYPE_PRIMARY }, > + { .base = 0x00, .phy = &rk3036_win1_data, > + .type = DRM_PLANE_TYPE_CURSOR }, > +}; > + > +static const int rk3036_vop_intrs[] = { > + DSP_HOLD_VALID_INTR, > + FS_INTR, > + LINE_FLAG_INTR, > + BUS_ERROR_INTR, > +}; > + > +static const struct vop_intr rk3036_intr = { > + .intrs = rk3036_vop_intrs, > + .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > + .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > + .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > + .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > +}; > + > +static const struct vop_ctrl rk3036_ctrl_data = { > + .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > + .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > + .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > + .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > + .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > + .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > + .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > + .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > +}; > + > +static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > + {RK3036_DSP_CTRL1, 0x00000000}, > +}; > + > +static const struct vop_data rk3036_vop = { > + .init_table = rk3036_vop_init_reg_table, > + .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > + .ctrl = &rk3036_ctrl_data, > + .intr = &rk3036_intr, > + .win = rk3036_vop_win_data, > + .win_size = ARRAY_SIZE(rk3036_vop_win_data), > +}; > + > static const struct vop_scl_extension rk3288_win_full_scl_ext = { > .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31), > .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30), > @@ -190,93 +272,11 @@ static const struct vop_data rk3288_vop = { > .win_size = ARRAY_SIZE(rk3288_vop_win_data), > }; > > -static const struct vop_scl_regs rk3036_win_scl = { > - .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0), > - .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16), > - .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0), > - .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win0_data = { > - .scl = &rk3036_win_scl, > - .data_formats = formats_win_full, > - .nformats = ARRAY_SIZE(formats_win_full), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15), > - .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0), > - .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0), > - .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16), > -}; > - > -static const struct vop_win_phy rk3036_win1_data = { > - .data_formats = formats_win_lite, > - .nformats = ARRAY_SIZE(formats_win_lite), > - .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1), > - .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6), > - .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19), > - .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0), > - .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0), > - .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0), > - .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0), > - .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0), > -}; > - > -static const struct vop_win_data rk3036_vop_win_data[] = { > - { .base = 0x00, .phy = &rk3036_win0_data, > - .type = DRM_PLANE_TYPE_PRIMARY }, > - { .base = 0x00, .phy = &rk3036_win1_data, > - .type = DRM_PLANE_TYPE_CURSOR }, > -}; > - > -static const int rk3036_vop_intrs[] = { > - DSP_HOLD_VALID_INTR, > - FS_INTR, > - LINE_FLAG_INTR, > - BUS_ERROR_INTR, > -}; > - > -static const struct vop_intr rk3036_intr = { > - .intrs = rk3036_vop_intrs, > - .nintrs = ARRAY_SIZE(rk3036_vop_intrs), > - .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0), > - .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4), > - .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8), > -}; > - > -static const struct vop_ctrl rk3036_ctrl_data = { > - .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30), > - .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0), > - .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4), > - .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0), > - .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0), > - .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0), > - .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0), > - .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0), > -}; > - > -static const struct vop_reg_data rk3036_vop_init_reg_table[] = { > - {RK3036_DSP_CTRL1, 0x00000000}, > -}; > - > -static const struct vop_data rk3036_vop = { > - .init_table = rk3036_vop_init_reg_table, > - .table_size = ARRAY_SIZE(rk3036_vop_init_reg_table), > - .ctrl = &rk3036_ctrl_data, > - .intr = &rk3036_intr, > - .win = rk3036_vop_win_data, > - .win_size = ARRAY_SIZE(rk3036_vop_win_data), > -}; > - > static const struct of_device_id vop_driver_dt_match[] = { > - { .compatible = "rockchip,rk3288-vop", > - .data = &rk3288_vop }, > { .compatible = "rockchip,rk3036-vop", > .data = &rk3036_vop }, > + { .compatible = "rockchip,rk3288-vop", > + .data = &rk3288_vop }, > {}, > }; > MODULE_DEVICE_TABLE(of, vop_driver_dt_match); -- Ｍark Yao