From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH v6 2/2] mfd: Add Samsung Exynos Low Power Audio Subsystem driver Date: Fri, 19 Aug 2016 10:32:31 +0900 Message-ID: <57B661AF.8010102@samsung.com> References: <1470840500-2428-1-git-send-email-s.nawrocki@samsung.com> <1470840500-2428-2-git-send-email-s.nawrocki@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) by alsa0.perex.cz (Postfix) with ESMTP id E4FFD2664B2 for ; Fri, 19 Aug 2016 03:32:34 +0200 (CEST) Received: from epcpsbgr2.samsung.com (u142.gpu120.samsung.co.kr [203.254.230.142]) by mailout3.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OC40004SUY7ABB0@mailout3.samsung.com> for alsa-devel@alsa-project.org; Fri, 19 Aug 2016 10:32:31 +0900 (KST) In-reply-to: <1470840500-2428-2-git-send-email-s.nawrocki@samsung.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org To: Sylwester Nawrocki , lee.jones@linaro.org Cc: robh@kernel.org, alsa-devel@alsa-project.org, linux-samsung-soc@vger.kernel.org, b.zolnierkie@samsung.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, broonie@kernel.org, Beomho Seo , Inha Song List-Id: alsa-devel@alsa-project.org RGVhciBhbGwsCgpJIHRlc3RlZCB0aGlzIHBhdGNoIHdpdGggVE0yIGR0IHBhdGNoZXNbMV0gYmFz ZWQgb24gdjQuOC1yYzIuClRvIHRlc3QgdGhlIHBsYXliYWNrLCBJIGFkanVzdCB0aGUgZHQgbm9k ZSBhY2NvcmRpbmcgdG8gTFBBU1MgZG9jdW1lbnRhdGlvbi4KWzFdIGh0dHBzOi8vbGttbC5vcmcv bGttbC8yMDE2LzgvMTYvNjEKICAgIFtQQVRDSCAwLzddIGFybTY0OiBkdHM6IEFkZCB0aGUgZHRz IGZpbGUgZm9yIEV4eW5vczU0MzMgYW5kIFRNL1RNMkUgYm9hcmQKClRlc3RlZC1ieTogQ2hhbndv byBDaG9pIDxjdzAwLmNob2lAc2Ftc3VuZy5jb20+CgpSZWdhcmRzLApDaGFud29vIENob2kKCk9u IDIwMTbrhYQgMDjsm5QgMTDsnbwgMjM6NDgsIFN5bHdlc3RlciBOYXdyb2NraSB3cm90ZToKPiBU aGlzIHBhdGNoIGFkZHMgY29tbW9uIGRyaXZlciBmb3IgdGhlIFRvcCBibG9jayBvZiB0aGUgU2Ft c3VuZyBFeHlub3MKPiBTb0MgTG93IFBvd2VyIEF1ZGlvIFN1YnN5c3RlbS4gIFRoaXMgaXMgYSBt aW5pbWFsIGRyaXZlciB3aGljaCBwcmVwYXJlcwo+IHJlc291cmNlcyBmb3IgSVAgYmxvY2tzIGxp a2UgSTJTLCBhdWRpbyBETUEgYW5kIFVBUlQgYW5kIGV4cG9zZXMKPiBhIHJlZ21hcCBmb3IgdGhl IFRvcCBibG9jayByZWdpc3RlcnMuICBBbHNvIHN5c3RlbSBwb3dlciBvcHMgYXJlIGFkZGVkCj4g dG8gZW5zdXJlIHRoZSBBdWRpbyBTdWJzeXN0ZW0gaXMgb3BlcmF0aW9uYWwgYWZ0ZXIgc3lzdGVt IHN1c3BlbmQvcmVzdW1lCj4gY3ljbGUuCj4gCj4gU2lnbmVkLW9mZi1ieTogSW5oYSBTb25nIDxp ZGVhbC5zb25nQHNhbXN1bmcuY29tPgo+IFNpZ25lZC1vZmYtYnk6IEJlb21obyBTZW8gPGJlb21o by5zZW9Ac2Ftc3VuZy5jb20+Cj4gU2lnbmVkLW9mZi1ieTogU3lsd2VzdGVyIE5hd3JvY2tpIDxz Lm5hd3JvY2tpQHNhbXN1bmcuY29tPgo+IC0tLQo+IAo+IENoYW5nZXMgc2luY2UgdjU6Cj4gIC0g QklUKCkgdXNlZCBmb3IgdGhlIHJlZ2lzdGVyIGJpdCBtYWNybyBkZWZpbml0aW9ucywKPiAgLSBy ZW1vdmVkIHVubmVlZGVkIGRldi0+b2Zfbm9kZSB0ZXN0LAo+ICAtIGV4eW5vc19scGFzc197c3Vz cGVuZCxyZXN1bWV9IGZ1bmN0aW9ucyBjb21waWxlZC1pbiBjb25kaXRpb25hbGx5LAo+ICAtIGFk ZGVkIGNvbW1lbnRzIGZvciBzdHJ1Y3QgZXh5bm9zX2xwYXNzIGZpZWxkcy4KPiAKPiBDaGFuZ2Vz IHNpbmNlIHY0Ogo+ICAtIG5vbmUuCj4gCj4gQ2hhbmdlcyBzaW5jZSB2MzoKPiAgLSBtb3ZlZCBm cm9tIHNvdW5kL3NvYy9zYW1zdW5nIGFuZCByZXdyaXR0ZW4gYXMgYSBNRkQgZHJpdmVyLAo+ICAt IFBNVSByZWdpc3RlciBkZWZpbml0aW9ucyBtb3ZlZCB0byBpbmNsdWRlL2xpbnV4L21mZC9zeXNj b24vZXh5bm9zNS1wbXUuaCwKPiAgLSBhZGRlZCByZWdtYXAgZm9yIExQQVNTIFRvcCBTRlIgcmVn aW9uLAo+ICAtIGNsZWFuZWQgdXAgcmVnaXN0ZXIgYml0IGZpZWxkIGRlZmludGlvbnMuCj4gCj4g Q2hhbmdlcyBzaW5jZSB2MjoKPiAgLSBtb3ZlIG1pc3BsYWNlZCBTTkRfU0FNU1VOR19BVURTUyBL Y29uZmlnIHN5bWJvbCBhZGRpdGlvbgo+ICAgIHRvIHRoaXMgcGF0Y2guCj4gLS0tCj4gIGRyaXZl cnMvbWZkL0tjb25maWcgICAgICAgICAgICAgICAgICAgIHwgICA4ICsrCj4gIGRyaXZlcnMvbWZk L01ha2VmaWxlICAgICAgICAgICAgICAgICAgIHwgICAxICsKPiAgZHJpdmVycy9tZmQvZXh5bm9z LWxwYXNzLmMgICAgICAgICAgICAgfCAxODcgKysrKysrKysrKysrKysrKysrKysrKysrKysrKysr KysrCj4gIGluY2x1ZGUvbGludXgvbWZkL3N5c2Nvbi9leHlub3M1LXBtdS5oIHwgICA0ICstCj4g IDQgZmlsZXMgY2hhbmdlZCwgMTk5IGluc2VydGlvbnMoKyksIDEgZGVsZXRpb24oLSkKPiAgY3Jl YXRlIG1vZGUgMTAwNjQ0IGRyaXZlcnMvbWZkL2V4eW5vcy1scGFzcy5jCj4gCj4gZGlmZiAtLWdp dCBhL2RyaXZlcnMvbWZkL0tjb25maWcgYi9kcml2ZXJzL21mZC9LY29uZmlnCj4gaW5kZXggMmQx ZmI2NC4uYTdlYzg5MCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL21mZC9LY29uZmlnCj4gKysrIGIv ZHJpdmVycy9tZmQvS2NvbmZpZwo+IEBAIC0yODEsNiArMjgxLDE0IEBAIGNvbmZpZyBNRkRfRExO Mgo+ICAJICBldGMuIG11c3QgYmUgZW5hYmxlZCBpbiBvcmRlciB0byB1c2UgdGhlIGZ1bmN0aW9u YWxpdHkgb2YKPiAgCSAgdGhlIGRldmljZS4KPiAgCj4gK2NvbmZpZyBNRkRfRVhZTk9TX0xQQVNT Cj4gKwl0cmlzdGF0ZSAiU2Ftc3VuZyBFeHlub3MgU29DIExvdyBQb3dlciBBdWRpbyBTdWJzeXN0 ZW0iCj4gKwlzZWxlY3QgTUZEX0NPUkUKPiArCXNlbGVjdCBSRUdNQVBfTU1JTwo+ICsJaGVscAo+ ICsJICBTZWxlY3QgdGhpcyBvcHRpb24gdG8gZW5hYmxlIHN1cHBvcnQgZm9yIFNhbXN1bmcgRXh5 bm9zIExvdyBQb3dlcgo+ICsJICBBdWRpbyBTdWJzeXN0ZW0uCj4gKwo+ICBjb25maWcgTUZEX01D MTNYWFgKPiAgCXRyaXN0YXRlCj4gIAlkZXBlbmRzIG9uIChTUElfTUFTVEVSIHx8IEkyQykKPiBk aWZmIC0tZ2l0IGEvZHJpdmVycy9tZmQvTWFrZWZpbGUgYi9kcml2ZXJzL21mZC9NYWtlZmlsZQo+ IGluZGV4IDJiYTNiYTMuLjQxNTEwYmIgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9tZmQvTWFrZWZp bGUKPiArKysgYi9kcml2ZXJzL21mZC9NYWtlZmlsZQo+IEBAIC0xMyw2ICsxMyw3IEBAIG9iai0k KENPTkZJR19NRkRfQkNNNTkwWFgpCSs9IGJjbTU5MHh4Lm8KPiAgb2JqLSQoQ09ORklHX01GRF9D Uk9TX0VDKQkrPSBjcm9zX2VjLm8KPiAgb2JqLSQoQ09ORklHX01GRF9DUk9TX0VDX0kyQykJKz0g Y3Jvc19lY19pMmMubwo+ICBvYmotJChDT05GSUdfTUZEX0NST1NfRUNfU1BJKQkrPSBjcm9zX2Vj X3NwaS5vCj4gK29iai0kKENPTkZJR19NRkRfRVhZTk9TX0xQQVNTKQkrPSBleHlub3MtbHBhc3Mu bwo+ICAKPiAgcnRzeF9wY2ktb2JqcwkJCTo9IHJ0c3hfcGNyLm8gcnRzNTIwOS5vIHJ0czUyMjku byBydGw4NDExLm8gcnRzNTIyNy5vIHJ0czUyNDkubwo+ICBvYmotJChDT05GSUdfTUZEX1JUU1hf UENJKQkrPSBydHN4X3BjaS5vCj4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvbWZkL2V4eW5vcy1scGFz cy5jIGIvZHJpdmVycy9tZmQvZXh5bm9zLWxwYXNzLmMKPiBuZXcgZmlsZSBtb2RlIDEwMDY0NAo+ IGluZGV4IDAwMDAwMDAuLjU3OGFjN2IKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvZHJpdmVycy9t ZmQvZXh5bm9zLWxwYXNzLmMKPiBAQCAtMCwwICsxLDE4NyBAQAo+ICsvKgo+ICsgKiBDb3B5cmln aHQgKEMpIDIwMTUgLSAyMDE2IFNhbXN1bmcgRWxlY3Ryb25pY3MgQ28uLCBMdGQuCj4gKyAqCj4g KyAqIEF1dGhvcnM6IEluaGEgU29uZyA8aWRlYWwuc29uZ0BzYW1zdW5nLmNvbT4KPiArICogICAg ICAgICAgU3lsd2VzdGVyIE5hd3JvY2tpIDxzLm5hd3JvY2tpQHNhbXN1bmcuY29tPgo+ICsgKgo+ ICsgKiBTYW1zdW5nIEV4eW5vcyBTb0Mgc2VyaWVzIExvdyBQb3dlciBBdWRpbyBTdWJzeXN0ZW0g ZHJpdmVyLgo+ICsgKgo+ICsgKiBUaGlzIG1vZHVsZSBwcm92aWRlcyByZWdtYXAgZm9yIHRoZSBU b3AgU0ZSIHJlZ2lvbiBhbmQgaW5zdGFudGlhdGVzCj4gKyAqIGRldmljZXMgZm9yIElQIGJsb2Nr cyBsaWtlIERNQUMsIEkyUywgVUFSVC4KPiArICoKPiArICogVGhpcyBwcm9ncmFtIGlzIGZyZWUg c29mdHdhcmU7IHlvdSBjYW4gcmVkaXN0cmlidXRlIGl0IGFuZC9vciBtb2RpZnkKPiArICogaXQg dW5kZXIgdGhlIHRlcm1zIG9mIHRoZSBHTlUgR2VuZXJhbCBQdWJsaWMgTGljZW5zZSB2ZXJzaW9u IDIgYW5kCj4gKyAqIG9ubHkgdmVyc2lvbiAyIGFzIHB1Ymxpc2hlZCBieSB0aGUgRnJlZSBTb2Z0 d2FyZSBGb3VuZGF0aW9uLgo+ICsgKi8KPiArCj4gKyNpbmNsdWRlIDxsaW51eC9kZWxheS5oPgo+ ICsjaW5jbHVkZSA8bGludXgvaW8uaD4KPiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+ICsj aW5jbHVkZSA8bGludXgvbWZkL3N5c2Nvbi5oPgo+ICsjaW5jbHVkZSA8bGludXgvbWZkL3N5c2Nv bi9leHlub3M1LXBtdS5oPgo+ICsjaW5jbHVkZSA8bGludXgvb2YuaD4KPiArI2luY2x1ZGUgPGxp bnV4L29mX3BsYXRmb3JtLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9wbGF0Zm9ybV9kZXZpY2UuaD4K PiArI2luY2x1ZGUgPGxpbnV4L3JlZ21hcC5oPgo+ICsjaW5jbHVkZSA8bGludXgvdHlwZXMuaD4K PiArCj4gKy8qIExQQVNTIFRvcCByZWdpc3RlciBkZWZpbml0aW9ucyAqLwo+ICsjZGVmaW5lIFNG Ul9MUEFTU19DT1JFX1NXX1JFU0VUCQkweDA4Cj4gKyNkZWZpbmUgIExQQVNTX1NCX1NXX1JFU0VU CQlCSVQoMTEpCj4gKyNkZWZpbmUgIExQQVNTX1VBUlRfU1dfUkVTRVQJCUJJVCgxMCkKPiArI2Rl ZmluZSAgTFBBU1NfUENNX1NXX1JFU0VUCQlCSVQoOSkKPiArI2RlZmluZSAgTFBBU1NfSTJTX1NX X1JFU0VUCQlCSVQoOCkKPiArI2RlZmluZSAgTFBBU1NfV0RUMV9TV19SRVNFVAkJQklUKDQpCj4g KyNkZWZpbmUgIExQQVNTX1dEVDBfU1dfUkVTRVQJCUJJVCgzKQo+ICsjZGVmaW5lICBMUEFTU19U SU1FUl9TV19SRVNFVAkJQklUKDIpCj4gKyNkZWZpbmUgIExQQVNTX01FTV9TV19SRVNFVAkJQklU KDEpCj4gKyNkZWZpbmUgIExQQVNTX0RNQV9TV19SRVNFVAkJQklUKDApCj4gKwo+ICsjZGVmaW5l IFNGUl9MUEFTU19JTlRSX0NBNV9NQVNLCQkweDQ4Cj4gKyNkZWZpbmUgU0ZSX0xQQVNTX0lOVFJf Q1BVX01BU0sJCTB4NTgKPiArI2RlZmluZSAgTFBBU1NfSU5UUl9BUE0JCQlCSVQoOSkKPiArI2Rl ZmluZSAgTFBBU1NfSU5UUl9NSUYJCQlCSVQoOCkKPiArI2RlZmluZSAgTFBBU1NfSU5UUl9USU1F UgkJQklUKDcpCj4gKyNkZWZpbmUgIExQQVNTX0lOVFJfRE1BCQkJQklUKDYpCj4gKyNkZWZpbmUg IExQQVNTX0lOVFJfR1BJTwkJQklUKDUpCj4gKyNkZWZpbmUgIExQQVNTX0lOVFJfSTJTCQkJQklU KDQpCj4gKyNkZWZpbmUgIExQQVNTX0lOVFJfUENNCQkJQklUKDMpCj4gKyNkZWZpbmUgIExQQVNT X0lOVFJfU0xJTUJVUwkJQklUKDIpCj4gKyNkZWZpbmUgIExQQVNTX0lOVFJfVUFSVAkJQklUKDEp Cj4gKyNkZWZpbmUgIExQQVNTX0lOVFJfU0ZSCQkJQklUKDApCj4gKwo+ICtzdHJ1Y3QgZXh5bm9z X2xwYXNzIHsKPiArCS8qIHBvaW50ZXIgdG8gdGhlIFBvd2VyIE1hbmFnZW1lbnQgVW5pdCByZWdt YXAgKi8KPiArCXN0cnVjdCByZWdtYXAgKnBtdTsKPiArCS8qIHBvaW50ZXIgdG8gdGhlIExQQVNT IFRPUCByZWdtYXAgKi8KPiArCXN0cnVjdCByZWdtYXAgKnRvcDsKPiArfTsKPiArCj4gK3N0YXRp YyB2b2lkIGV4eW5vc19scGFzc19jb3JlX3N3X3Jlc2V0KHN0cnVjdCBleHlub3NfbHBhc3MgKmxw YXNzLCBpbnQgbWFzaykKPiArewo+ICsJdW5zaWduZWQgaW50IHZhbCA9IDA7Cj4gKwo+ICsJcmVn bWFwX3JlYWQobHBhc3MtPnRvcCwgU0ZSX0xQQVNTX0NPUkVfU1dfUkVTRVQsICZ2YWwpOwo+ICsK PiArCXZhbCAmPSB+bWFzazsKPiArCXJlZ21hcF93cml0ZShscGFzcy0+dG9wLCBTRlJfTFBBU1Nf Q09SRV9TV19SRVNFVCwgdmFsKTsKPiArCj4gKwl1c2xlZXBfcmFuZ2UoMTAwLCAxNTApOwo+ICsK PiArCXZhbCB8PSBtYXNrOwo+ICsJcmVnbWFwX3dyaXRlKGxwYXNzLT50b3AsIFNGUl9MUEFTU19D T1JFX1NXX1JFU0VULCB2YWwpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCBleHlub3NfbHBhc3Nf ZW5hYmxlKHN0cnVjdCBleHlub3NfbHBhc3MgKmxwYXNzKQo+ICt7Cj4gKwkvKiBVbm1hc2sgU0ZS LCBETUEgYW5kIEkyUyBpbnRlcnJ1cHQgKi8KPiArCXJlZ21hcF93cml0ZShscGFzcy0+dG9wLCBT RlJfTFBBU1NfSU5UUl9DQTVfTUFTSywKPiArCQkgICAgIExQQVNTX0lOVFJfU0ZSIHwgTFBBU1Nf SU5UUl9ETUEgfCBMUEFTU19JTlRSX0kyUyk7Cj4gKwo+ICsJcmVnbWFwX3dyaXRlKGxwYXNzLT50 b3AsIFNGUl9MUEFTU19JTlRSX0NQVV9NQVNLLAo+ICsJCSAgICAgTFBBU1NfSU5UUl9TRlIgfCBM UEFTU19JTlRSX0RNQSB8IExQQVNTX0lOVFJfSTJTKTsKPiArCj4gKwkvKiBBY3RpdmF0ZSByZWxh dGVkIFBBRHMgZnJvbSByZXRlbnRpb24gc3RhdGUgKi8KPiArCXJlZ21hcF93cml0ZShscGFzcy0+ cG11LCBFWFlOT1M1NDMzX1BBRF9SRVRFTlRJT05fQVVEX09QVElPTiwKPiArCQkgICAgIEVYWU5P UzU0MzNfUEFEX0lOSVRJQVRFX1dBS0VVUF9GUk9NX0xPV1BXUik7Cj4gKwo+ICsJZXh5bm9zX2xw YXNzX2NvcmVfc3dfcmVzZXQobHBhc3MsIExQQVNTX0kyU19TV19SRVNFVCk7Cj4gKwlleHlub3Nf bHBhc3NfY29yZV9zd19yZXNldChscGFzcywgTFBBU1NfRE1BX1NXX1JFU0VUKTsKPiArCWV4eW5v c19scGFzc19jb3JlX3N3X3Jlc2V0KGxwYXNzLCBMUEFTU19NRU1fU1dfUkVTRVQpOwo+ICt9Cj4g Kwo+ICtzdGF0aWMgdm9pZCBleHlub3NfbHBhc3NfZGlzYWJsZShzdHJ1Y3QgZXh5bm9zX2xwYXNz ICpscGFzcykKPiArewo+ICsJLyogTWFzayBhbnkgdW5tYXNrZWQgSVAgaW50ZXJydXB0IHNvdXJj ZXMgKi8KPiArCXJlZ21hcF93cml0ZShscGFzcy0+dG9wLCBTRlJfTFBBU1NfSU5UUl9DUFVfTUFT SywgMCk7Cj4gKwlyZWdtYXBfd3JpdGUobHBhc3MtPnRvcCwgU0ZSX0xQQVNTX0lOVFJfQ0E1X01B U0ssIDApOwo+ICsKPiArCS8qIERlYWN0aXZhdGUgcmVsYXRlZCBQQURzIGZyb20gcmV0ZW50aW9u IHN0YXRlICovCj4gKwlyZWdtYXBfd3JpdGUobHBhc3MtPnBtdSwgRVhZTk9TNTQzM19QQURfUkVU RU5USU9OX0FVRF9PUFRJT04sIDApOwo+ICt9Cj4gKwo+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHJl Z21hcF9jb25maWcgZXh5bm9zX2xwYXNzX3JlZ19jb25mID0gewo+ICsJLnJlZ19iaXRzCT0gMzIs Cj4gKwkucmVnX3N0cmlkZQk9IDQsCj4gKwkudmFsX2JpdHMJPSAzMiwKPiArCS5tYXhfcmVnaXN0 ZXIJPSAweGZjLAo+ICsJLmZhc3RfaW8JPSB0cnVlLAo+ICt9Owo+ICsKPiArc3RhdGljIGludCBl eHlub3NfbHBhc3NfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJ c3RydWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiArCXN0cnVjdCBleHlub3NfbHBhc3Mg KmxwYXNzOwo+ICsJdm9pZCBfX2lvbWVtICpiYXNlX3RvcDsKPiArCXN0cnVjdCByZXNvdXJjZSAq cmVzOwo+ICsKPiArCWxwYXNzID0gZGV2bV9remFsbG9jKGRldiwgc2l6ZW9mKCpscGFzcyksIEdG UF9LRVJORUwpOwo+ICsJaWYgKCFscGFzcykKPiArCQlyZXR1cm4gLUVOT01FTTsKPiArCj4gKwly ZXMgPSBwbGF0Zm9ybV9nZXRfcmVzb3VyY2UocGRldiwgSU9SRVNPVVJDRV9NRU0sIDApOwo+ICsJ YmFzZV90b3AgPSBkZXZtX2lvcmVtYXBfcmVzb3VyY2UoZGV2LCByZXMpOwo+ICsJaWYgKElTX0VS UihiYXNlX3RvcCkpCj4gKwkJcmV0dXJuIFBUUl9FUlIoYmFzZV90b3ApOwo+ICsKPiArCWxwYXNz LT50b3AgPSByZWdtYXBfaW5pdF9tbWlvKGRldiwgYmFzZV90b3AsCj4gKwkJCQkJJmV4eW5vc19s cGFzc19yZWdfY29uZik7Cj4gKwlpZiAoSVNfRVJSKGxwYXNzLT50b3ApKSB7Cj4gKwkJZGV2X2Vy cihkZXYsICJMUEFTUyB0b3AgcmVnbWFwIGluaXRpYWxpemF0aW9uIGZhaWxlZFxuIik7Cj4gKwkJ cmV0dXJuIFBUUl9FUlIobHBhc3MtPnRvcCk7Cj4gKwl9Cj4gKwo+ICsJbHBhc3MtPnBtdSA9IHN5 c2Nvbl9yZWdtYXBfbG9va3VwX2J5X3BoYW5kbGUoZGV2LT5vZl9ub2RlLAo+ICsJCQkJCQkic2Ft c3VuZyxwbXUtc3lzY29uIik7Cj4gKwlpZiAoSVNfRVJSKGxwYXNzLT5wbXUpKSB7Cj4gKwkJZGV2 X2VycihkZXYsICJGYWlsZWQgdG8gbG9va3VwIFBNVSByZWdtYXBcbiIpOwo+ICsJCXJldHVybiBQ VFJfRVJSKGxwYXNzLT5wbXUpOwo+ICsJfQo+ICsKPiArCXBsYXRmb3JtX3NldF9kcnZkYXRhKHBk ZXYsIGxwYXNzKTsKPiArCWV4eW5vc19scGFzc19lbmFibGUobHBhc3MpOwo+ICsKPiArCXJldHVy biBvZl9wbGF0Zm9ybV9wb3B1bGF0ZShkZXYtPm9mX25vZGUsIE5VTEwsIE5VTEwsIGRldik7Cj4g K30KPiArCj4gKyNpZmRlZiBDT05GSUdfUE1fU0xFRVAKPiArc3RhdGljIGludCBleHlub3NfbHBh c3Nfc3VzcGVuZChzdHJ1Y3QgZGV2aWNlICpkZXYpCj4gK3sKPiArCXN0cnVjdCBleHlub3NfbHBh c3MgKmxwYXNzID0gZGV2X2dldF9kcnZkYXRhKGRldik7Cj4gKwo+ICsJZXh5bm9zX2xwYXNzX2Rp c2FibGUobHBhc3MpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IGV4 eW5vc19scGFzc19yZXN1bWUoc3RydWN0IGRldmljZSAqZGV2KQo+ICt7Cj4gKwlzdHJ1Y3QgZXh5 bm9zX2xwYXNzICpscGFzcyA9IGRldl9nZXRfZHJ2ZGF0YShkZXYpOwo+ICsKPiArCWV4eW5vc19s cGFzc19lbmFibGUobHBhc3MpOwo+ICsKPiArCXJldHVybiAwOwo+ICt9Cj4gKyNlbmRpZgo+ICsK PiArc3RhdGljIFNJTVBMRV9ERVZfUE1fT1BTKGxwYXNzX3BtX29wcywgZXh5bm9zX2xwYXNzX3N1 c3BlbmQsCj4gKwkJCQkJZXh5bm9zX2xwYXNzX3Jlc3VtZSk7Cj4gKwo+ICtzdGF0aWMgY29uc3Qg c3RydWN0IG9mX2RldmljZV9pZCBleHlub3NfbHBhc3Nfb2ZfbWF0Y2hbXSA9IHsKPiArCXsgLmNv bXBhdGlibGUgPSAic2Ftc3VuZyxleHlub3M1NDMzLWxwYXNzIiB9LAo+ICsJeyB9LAo+ICt9Owo+ ICtNT0RVTEVfREVWSUNFX1RBQkxFKG9mLCBleHlub3NfbHBhc3Nfb2ZfbWF0Y2gpOwo+ICsKPiAr c3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgZXh5bm9zX2xwYXNzX2RyaXZlciA9IHsKPiAr CS5kcml2ZXIgPSB7Cj4gKwkJLm5hbWUJCT0gImV4eW5vcy1scGFzcyIsCj4gKwkJLnBtCQk9ICZs cGFzc19wbV9vcHMsCj4gKwkJLm9mX21hdGNoX3RhYmxlCT0gZXh5bm9zX2xwYXNzX29mX21hdGNo LAo+ICsJfSwKPiArCS5wcm9iZQk9IGV4eW5vc19scGFzc19wcm9iZSwKPiArfTsKPiArbW9kdWxl X3BsYXRmb3JtX2RyaXZlcihleHlub3NfbHBhc3NfZHJpdmVyKTsKPiArCj4gK01PRFVMRV9ERVND UklQVElPTigiU2Ftc3VuZyBMb3cgUG93ZXIgQXVkaW8gU3Vic3lzdGVtIGRyaXZlciIpOwo+ICtN T0RVTEVfTElDRU5TRSgiR1BMIHYyIik7Cj4gZGlmZiAtLWdpdCBhL2luY2x1ZGUvbGludXgvbWZk L3N5c2Nvbi9leHlub3M1LXBtdS5oIGIvaW5jbHVkZS9saW51eC9tZmQvc3lzY29uL2V4eW5vczUt cG11LmgKPiBpbmRleCA3NmYzMGY5Li5jMjhmZjIxIDEwMDY0NAo+IC0tLSBhL2luY2x1ZGUvbGlu dXgvbWZkL3N5c2Nvbi9leHlub3M1LXBtdS5oCj4gKysrIGIvaW5jbHVkZS9saW51eC9tZmQvc3lz Y29uL2V4eW5vczUtcG11LmgKPiBAQCAtNDMsOCArNDMsMTAgQEAKPiAgI2RlZmluZSBFWFlOT1M1 NDMzX01JUElfUEhZMl9DT05UUk9MCQkoMHg3MTgpCj4gIAo+ICAjZGVmaW5lIEVYWU5PUzVfUEhZ X0VOQUJMRQkJCUJJVCgwKQo+IC0KPiAgI2RlZmluZSBFWFlOT1M1X01JUElfUEhZX1NfUkVTRVRO CQlCSVQoMSkKPiAgI2RlZmluZSBFWFlOT1M1X01JUElfUEhZX01fUkVTRVROCQlCSVQoMikKPiAg Cj4gKyNkZWZpbmUgRVhZTk9TNTQzM19QQURfUkVURU5USU9OX0FVRF9PUFRJT04JCSgweDMwMjgp Cj4gKyNkZWZpbmUgRVhZTk9TNTQzM19QQURfSU5JVElBVEVfV0FLRVVQX0ZST01fTE9XUFdSCUJJ VCgyOCkKPiArCj4gICNlbmRpZiAvKiBfTElOVVhfTUZEX1NZU0NPTl9QTVVfRVhZTk9TNV9IXyAq Lwo+IAoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KQWxz YS1kZXZlbCBtYWlsaW5nIGxpc3QKQWxzYS1kZXZlbEBhbHNhLXByb2plY3Qub3JnCmh0dHA6Ly9t YWlsbWFuLmFsc2EtcHJvamVjdC5vcmcvbWFpbG1hbi9saXN0aW5mby9hbHNhLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754878AbcHSBdS (ORCPT ); Thu, 18 Aug 2016 21:33:18 -0400 Received: from mailout3.samsung.com ([203.254.224.33]:55458 "EHLO mailout3.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754387AbcHSBdI (ORCPT ); Thu, 18 Aug 2016 21:33:08 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee68e-f79cb6d000006cfe-5e-57b661af1636 Content-transfer-encoding: 8BIT Message-id: <57B661AF.8010102@samsung.com> Date: Fri, 19 Aug 2016 10:32:31 +0900 From: Chanwoo Choi Organization: Samsung Electronics User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Sylwester Nawrocki , lee.jones@linaro.org Cc: broonie@kernel.org, alsa-devel@alsa-project.org, robh@kernel.org, devicetree@vger.kernel.org, b.zolnierkie@samsung.com, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Inha Song , Beomho Seo Subject: Re: [PATCH v6 2/2] mfd: Add Samsung Exynos Low Power Audio Subsystem driver References: <1470840500-2428-1-git-send-email-s.nawrocki@samsung.com> <1470840500-2428-2-git-send-email-s.nawrocki@samsung.com> In-reply-to: <1470840500-2428-2-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrMIsWRmVeSWpSXmKPExsWyRsSkQHd94rZwg/kv9CyuXDzEZLFxxnpW i9OftrFbTH34hM1i/pFzrBa7/t5ntLj/9SijxeVdc9gsZpzfx2Txf88OdovDb9pZHbg9Nnxu YvPYtKqTzePOtT1sHn1bVjF6fN4kF8AaxWWTkpqTWZZapG+XwJVxeGcDY8Fk34ptt/8xNzDe tOti5OSQEDCRaJt5jBXCFpO4cG89WxcjF4eQwApGiZX3PzDBFK3pmsAEkZjFKLHv6yUWkASv gKDEj8n3gGwODmYBeYkjl7JBwswC6hKT5i1ihqh/wCgx+dEUZoh6LYlvpyeygdgsAqoSc9u2 gsXZgOL7X9wAi/MLKEpc/fGYEWSmqECERPeJSpCwiICrxObunWAzmQW6mCRO3F0F1issECbx 68cyVohlVxklGu/eB0twCrhJvN88GywhIdDIIdF6dx8jxGYBiW+TD4FdLSEgK7HpADPEl5IS B1fcYJnAKD4LyW+zEH6bheS3BYzMqxhFUwuSC4qT0ouM9IoTc4tL89L1kvNzNzEC4/b0v2d9 OxhvHrA+xCjAwajEw2vxfGu4EGtiWXFl7iFGU6AjJjJLiSbnA5NDXkm8obGZkYWpiamxkbml mZI4b4LUz2AhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjArhgp9CZ3GUMvjkCwp2xEvrVK7K jFedbaRxUb34xtHPVxVr7Bd1Xa9YmPbGUzr4muL6z9XZp6ZIW86Kt455LHGG4chSk/nB9/5E +YX/7//asL+oaPo/p5npxkkuQlOdzMqrkrwCCtc23ft49yT3pMw1r7dqfDy06Zpj15fgRAl7 57tq3sLHlViKMxINtZiLihMBs/LU3NYCAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAKsWRmVeSWpSXmKPExsVy+t9jQd31idvCDZ72q1tcuXiIyWLjjPWs Fqc/bWO3mPrwCZvF/CPnWC12/b3PaHH/61FGi8u75rBZzDi/j8ni/54d7BaH37SzOnB7bPjc xOaxaVUnm8eda3vYPPq2rGL0+LxJLoA1qoHRJiM1MSW1SCE1Lzk/JTMv3VbJOzjeOd7UzMBQ 19DSwlxJIS8xN9VWycUnQNctMwfoNiWFssScUqBQQGJxsZK+HaYJoSFuuhYwjRG6viFBcD1G BmggYQ1jxuGdDYwFk30rtt3+x9zAeNOui5GTQ0LARGJN1wQmCFtM4sK99WxdjFwcQgKzGCX2 fb3EApLgFRCU+DH5HpDNwcEsIC9x5FI2SJhZQF1i0rxFzBD1DxglJj+awgxRryXx7fRENhCb RUBVYm7bVrA4G1B8/4sbYHF+AUWJqz8eM4LMFBWIkOg+UQkSFhFwldjcvRNsJrNAF5PEibur wHqFBcIkfv1Yxgqx7CqjROPd+2AJTgE3ifebZ7NOYBScheTWWQi3zkJy6wJG5lWMEqkFyQXF Sem5hnmp5XrFibnFpXnpesn5uZsYwanhmdQOxoO73A8xCnAwKvHw7ji4NVyINbGsuDL3EKME B7OSCO/O+G3hQrwpiZVVqUX58UWlOanFhxhNgZ6dyCwlmpwPTFt5JfGGxiZmRpZG5oYWRsbm SuK8j/+vCxMSSE8sSc1OTS1ILYLpY+LglGpgXJpVPYmL59SW9KkVieuvZLSUfat//ik/+/ev 28umGQZMWX/JOLP0PtOsTOP388v12NlK7ETZG8/Nqvn4aeqd3ZyJRU1R1aEM3MoOHutYjI99 KNk+NbLim8TXf9VTfP5tdTO4wfaVMfrVRs5E/2lV4jLB83b+MAo9ov+0985Ja/P5+1liP210 VmIpzkg01GIuKk4EAJerBVcjAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Dear all, I tested this patch with TM2 dt patches[1] based on v4.8-rc2. To test the playback, I adjust the dt node according to LPASS documentation. [1] https://lkml.org/lkml/2016/8/16/61 [PATCH 0/7] arm64: dts: Add the dts file for Exynos5433 and TM/TM2E board Tested-by: Chanwoo Choi Regards, Chanwoo Choi On 2016년 08월 10일 23:48, Sylwester Nawrocki wrote: > This patch adds common driver for the Top block of the Samsung Exynos > SoC Low Power Audio Subsystem. This is a minimal driver which prepares > resources for IP blocks like I2S, audio DMA and UART and exposes > a regmap for the Top block registers. Also system power ops are added > to ensure the Audio Subsystem is operational after system suspend/resume > cycle. > > Signed-off-by: Inha Song > Signed-off-by: Beomho Seo > Signed-off-by: Sylwester Nawrocki > --- > > Changes since v5: > - BIT() used for the register bit macro definitions, > - removed unneeded dev->of_node test, > - exynos_lpass_{suspend,resume} functions compiled-in conditionally, > - added comments for struct exynos_lpass fields. > > Changes since v4: > - none. > > Changes since v3: > - moved from sound/soc/samsung and rewritten as a MFD driver, > - PMU register definitions moved to include/linux/mfd/syscon/exynos5-pmu.h, > - added regmap for LPASS Top SFR region, > - cleaned up register bit field defintions. > > Changes since v2: > - move misplaced SND_SAMSUNG_AUDSS Kconfig symbol addition > to this patch. > --- > drivers/mfd/Kconfig | 8 ++ > drivers/mfd/Makefile | 1 + > drivers/mfd/exynos-lpass.c | 187 +++++++++++++++++++++++++++++++++ > include/linux/mfd/syscon/exynos5-pmu.h | 4 +- > 4 files changed, 199 insertions(+), 1 deletion(-) > create mode 100644 drivers/mfd/exynos-lpass.c > > diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig > index 2d1fb64..a7ec890 100644 > --- a/drivers/mfd/Kconfig > +++ b/drivers/mfd/Kconfig > @@ -281,6 +281,14 @@ config MFD_DLN2 > etc. must be enabled in order to use the functionality of > the device. > > +config MFD_EXYNOS_LPASS > + tristate "Samsung Exynos SoC Low Power Audio Subsystem" > + select MFD_CORE > + select REGMAP_MMIO > + help > + Select this option to enable support for Samsung Exynos Low Power > + Audio Subsystem. > + > config MFD_MC13XXX > tristate > depends on (SPI_MASTER || I2C) > diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile > index 2ba3ba3..41510bb 100644 > --- a/drivers/mfd/Makefile > +++ b/drivers/mfd/Makefile > @@ -13,6 +13,7 @@ obj-$(CONFIG_MFD_BCM590XX) += bcm590xx.o > obj-$(CONFIG_MFD_CROS_EC) += cros_ec.o > obj-$(CONFIG_MFD_CROS_EC_I2C) += cros_ec_i2c.o > obj-$(CONFIG_MFD_CROS_EC_SPI) += cros_ec_spi.o > +obj-$(CONFIG_MFD_EXYNOS_LPASS) += exynos-lpass.o > > rtsx_pci-objs := rtsx_pcr.o rts5209.o rts5229.o rtl8411.o rts5227.o rts5249.o > obj-$(CONFIG_MFD_RTSX_PCI) += rtsx_pci.o > diff --git a/drivers/mfd/exynos-lpass.c b/drivers/mfd/exynos-lpass.c > new file mode 100644 > index 0000000..578ac7b > --- /dev/null > +++ b/drivers/mfd/exynos-lpass.c > @@ -0,0 +1,187 @@ > +/* > + * Copyright (C) 2015 - 2016 Samsung Electronics Co., Ltd. > + * > + * Authors: Inha Song > + * Sylwester Nawrocki > + * > + * Samsung Exynos SoC series Low Power Audio Subsystem driver. > + * > + * This module provides regmap for the Top SFR region and instantiates > + * devices for IP blocks like DMAC, I2S, UART. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* LPASS Top register definitions */ > +#define SFR_LPASS_CORE_SW_RESET 0x08 > +#define LPASS_SB_SW_RESET BIT(11) > +#define LPASS_UART_SW_RESET BIT(10) > +#define LPASS_PCM_SW_RESET BIT(9) > +#define LPASS_I2S_SW_RESET BIT(8) > +#define LPASS_WDT1_SW_RESET BIT(4) > +#define LPASS_WDT0_SW_RESET BIT(3) > +#define LPASS_TIMER_SW_RESET BIT(2) > +#define LPASS_MEM_SW_RESET BIT(1) > +#define LPASS_DMA_SW_RESET BIT(0) > + > +#define SFR_LPASS_INTR_CA5_MASK 0x48 > +#define SFR_LPASS_INTR_CPU_MASK 0x58 > +#define LPASS_INTR_APM BIT(9) > +#define LPASS_INTR_MIF BIT(8) > +#define LPASS_INTR_TIMER BIT(7) > +#define LPASS_INTR_DMA BIT(6) > +#define LPASS_INTR_GPIO BIT(5) > +#define LPASS_INTR_I2S BIT(4) > +#define LPASS_INTR_PCM BIT(3) > +#define LPASS_INTR_SLIMBUS BIT(2) > +#define LPASS_INTR_UART BIT(1) > +#define LPASS_INTR_SFR BIT(0) > + > +struct exynos_lpass { > + /* pointer to the Power Management Unit regmap */ > + struct regmap *pmu; > + /* pointer to the LPASS TOP regmap */ > + struct regmap *top; > +}; > + > +static void exynos_lpass_core_sw_reset(struct exynos_lpass *lpass, int mask) > +{ > + unsigned int val = 0; > + > + regmap_read(lpass->top, SFR_LPASS_CORE_SW_RESET, &val); > + > + val &= ~mask; > + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); > + > + usleep_range(100, 150); > + > + val |= mask; > + regmap_write(lpass->top, SFR_LPASS_CORE_SW_RESET, val); > +} > + > +static void exynos_lpass_enable(struct exynos_lpass *lpass) > +{ > + /* Unmask SFR, DMA and I2S interrupt */ > + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, > + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); > + > + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, > + LPASS_INTR_SFR | LPASS_INTR_DMA | LPASS_INTR_I2S); > + > + /* Activate related PADs from retention state */ > + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, > + EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR); > + > + exynos_lpass_core_sw_reset(lpass, LPASS_I2S_SW_RESET); > + exynos_lpass_core_sw_reset(lpass, LPASS_DMA_SW_RESET); > + exynos_lpass_core_sw_reset(lpass, LPASS_MEM_SW_RESET); > +} > + > +static void exynos_lpass_disable(struct exynos_lpass *lpass) > +{ > + /* Mask any unmasked IP interrupt sources */ > + regmap_write(lpass->top, SFR_LPASS_INTR_CPU_MASK, 0); > + regmap_write(lpass->top, SFR_LPASS_INTR_CA5_MASK, 0); > + > + /* Deactivate related PADs from retention state */ > + regmap_write(lpass->pmu, EXYNOS5433_PAD_RETENTION_AUD_OPTION, 0); > +} > + > +static const struct regmap_config exynos_lpass_reg_conf = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0xfc, > + .fast_io = true, > +}; > + > +static int exynos_lpass_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct exynos_lpass *lpass; > + void __iomem *base_top; > + struct resource *res; > + > + lpass = devm_kzalloc(dev, sizeof(*lpass), GFP_KERNEL); > + if (!lpass) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + base_top = devm_ioremap_resource(dev, res); > + if (IS_ERR(base_top)) > + return PTR_ERR(base_top); > + > + lpass->top = regmap_init_mmio(dev, base_top, > + &exynos_lpass_reg_conf); > + if (IS_ERR(lpass->top)) { > + dev_err(dev, "LPASS top regmap initialization failed\n"); > + return PTR_ERR(lpass->top); > + } > + > + lpass->pmu = syscon_regmap_lookup_by_phandle(dev->of_node, > + "samsung,pmu-syscon"); > + if (IS_ERR(lpass->pmu)) { > + dev_err(dev, "Failed to lookup PMU regmap\n"); > + return PTR_ERR(lpass->pmu); > + } > + > + platform_set_drvdata(pdev, lpass); > + exynos_lpass_enable(lpass); > + > + return of_platform_populate(dev->of_node, NULL, NULL, dev); > +} > + > +#ifdef CONFIG_PM_SLEEP > +static int exynos_lpass_suspend(struct device *dev) > +{ > + struct exynos_lpass *lpass = dev_get_drvdata(dev); > + > + exynos_lpass_disable(lpass); > + > + return 0; > +} > + > +static int exynos_lpass_resume(struct device *dev) > +{ > + struct exynos_lpass *lpass = dev_get_drvdata(dev); > + > + exynos_lpass_enable(lpass); > + > + return 0; > +} > +#endif > + > +static SIMPLE_DEV_PM_OPS(lpass_pm_ops, exynos_lpass_suspend, > + exynos_lpass_resume); > + > +static const struct of_device_id exynos_lpass_of_match[] = { > + { .compatible = "samsung,exynos5433-lpass" }, > + { }, > +}; > +MODULE_DEVICE_TABLE(of, exynos_lpass_of_match); > + > +static struct platform_driver exynos_lpass_driver = { > + .driver = { > + .name = "exynos-lpass", > + .pm = &lpass_pm_ops, > + .of_match_table = exynos_lpass_of_match, > + }, > + .probe = exynos_lpass_probe, > +}; > +module_platform_driver(exynos_lpass_driver); > + > +MODULE_DESCRIPTION("Samsung Low Power Audio Subsystem driver"); > +MODULE_LICENSE("GPL v2"); > diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h > index 76f30f9..c28ff21 100644 > --- a/include/linux/mfd/syscon/exynos5-pmu.h > +++ b/include/linux/mfd/syscon/exynos5-pmu.h > @@ -43,8 +43,10 @@ > #define EXYNOS5433_MIPI_PHY2_CONTROL (0x718) > > #define EXYNOS5_PHY_ENABLE BIT(0) > - > #define EXYNOS5_MIPI_PHY_S_RESETN BIT(1) > #define EXYNOS5_MIPI_PHY_M_RESETN BIT(2) > > +#define EXYNOS5433_PAD_RETENTION_AUD_OPTION (0x3028) > +#define EXYNOS5433_PAD_INITIATE_WAKEUP_FROM_LOWPWR BIT(28) > + > #endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */ >