Re: [PATCH v2 23/25] dt-bindings: display/msm: Remove power domain property from encoder nodes

[Archit Taneja <architt@codeaurora.org>]

Hi Rob,

On 06/23/2016 07:43 PM, Archit Taneja wrote:
> Remove the power-domain property from the DSI, HDMI and eDP dt-binding
> docs. The power domain only needs to be specified in the parent MDSS
> device node (that too only for SoCs which contain MDSS).

Can I get an Ack on this?

Thanks,
Archit

>
> Signed-off-by: Archit Taneja <architt@codeaurora.org>
> ---
>   Documentation/devicetree/bindings/display/msm/dsi.txt  | 3 ---
>   Documentation/devicetree/bindings/display/msm/edp.txt  | 2 --
>   Documentation/devicetree/bindings/display/msm/hdmi.txt | 4 ----
>   3 files changed, 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
> index e6933a8..c1ef181 100644
> --- a/Documentation/devicetree/bindings/display/msm/dsi.txt
> +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
> @@ -8,7 +8,6 @@ Required properties:
>   - reg-names: The names of register regions. The following regions are required:
>     * "dsi_ctrl"
>   - interrupts: The interrupt signal from the DSI block.
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
>   - clocks: Phandles to device clocks.
>   - clock-names: the following clocks are required:
>     * "mdp_core_clk"
> @@ -94,7 +93,6 @@ Required properties:
>     * "dsi_phy_regulator"
>   - clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
>     2 clocks: A byte clock (index 0), and a pixel clock (index 1).
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
>   - clocks: Phandles to device clocks. See [1] for details on clock bindings.
>   - clock-names: the following clocks are required:
>     * "iface_clk"
> @@ -116,7 +114,6 @@ Example:
>   		interrupts = <4 0>;
>   		reg-names = "dsi_ctrl";
>   		reg = <0xfd922800 0x200>;
> -		power-domains = <&mmcc MDSS_GDSC>;
>   		clock-names =
>   			"bus_clk",
>   			"byte_clk",
> diff --git a/Documentation/devicetree/bindings/display/msm/edp.txt b/Documentation/devicetree/bindings/display/msm/edp.txt
> index 3a20f6e..e712dfa 100644
> --- a/Documentation/devicetree/bindings/display/msm/edp.txt
> +++ b/Documentation/devicetree/bindings/display/msm/edp.txt
> @@ -8,7 +8,6 @@ Required properties:
>     * "edp"
>     * "pll_base"
>   - interrupts: The interrupt signal from the eDP block.
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
>   - clocks: device clocks
>     See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
>   - clock-names: the following clocks are required:
> @@ -39,7 +38,6 @@ Example:
>   				<0xfd923a00 0xd4>;
>   			interrupt-parent = <&mdss_mdp>;
>   			interrupts = <12 0>;
> -			power-domains = <&mmcc MDSS_GDSC>;
>   			clock-names =
>   				"core_clk",
>   				"pixel_clk",
> diff --git a/Documentation/devicetree/bindings/display/msm/hdmi.txt b/Documentation/devicetree/bindings/display/msm/hdmi.txt
> index b63f614..ce84459 100644
> --- a/Documentation/devicetree/bindings/display/msm/hdmi.txt
> +++ b/Documentation/devicetree/bindings/display/msm/hdmi.txt
> @@ -11,7 +11,6 @@ Required properties:
>   - reg: Physical base address and length of the controller's registers
>   - reg-names: "core_physical"
>   - interrupts: The interrupt signal from the hdmi block.
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
>   - clocks: device clocks
>     See ../clocks/clock-bindings.txt for details.
>   - qcom,hdmi-tx-ddc-clk-gpio: ddc clk pin
> @@ -48,7 +47,6 @@ Required properties:
>       * "hdmi_tx_l1"
>       * "hdmi_tx_l3"
>       * "hdmi_tx_l4"
> -- power-domains: Should be <&mmcc MDSS_GDSC>.
>   - clocks: device clocks
>     See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
>   - core-vdda-supply: phandle to vdda regulator device node
> @@ -63,7 +61,6 @@ Example:
>   		reg-names = "core_physical";
>   		reg = <0x04a00000 0x2f0>;
>   		interrupts = <GIC_SPI 79 0>;
> -		power-domains = <&mmcc MDSS_GDSC>;
>   		clock-names =
>   		    "core_clk",
>   		    "master_iface_clk",
> @@ -92,7 +89,6 @@ Example:
>   		reg = <0x4a00400 0x60>,
>   		      <0x4a00500 0x100>;
>   		#phy-cells = <0>;
> -		power-domains = <&mmcc MDSS_GDSC>;
>   		clock-names = "slave_iface_clk";
>   		clocks = <&mmcc HDMI_S_AHB_CLK>;
>   		core-vdda-supply = <&pm8921_hdmi_mvs>;
>

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