All of lore.kernel.org
 help / color / mirror / Atom feed
diff for duplicates of <57C7B70C.3020101@ti.com>

diff --git a/a/1.txt b/N1/1.txt
index c35b441..11afbdb 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -8,7 +8,7 @@ On Wednesday 31 August 2016 07:38 PM, Heiko Stübner wrote:
 >> Access the PHY via registers provided by GRF (general register
 >> files) module.
 >>
->> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
+>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 > 
 > seems I'm late to the party, but when looking if I can apply the pcie-
 > devicetree patches, I found that the phy is still pending.
diff --git a/a/content_digest b/N1/content_digest
index 3a82270..47690d9 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -1,18 +1,18 @@
  "ref\01471661617-26432-1-git-send-email-shawn.lin@rock-chips.com\0"
  "ref\01471661617-26432-2-git-send-email-shawn.lin@rock-chips.com\0"
  "ref\06005500.MI6i4QbaFN@diego\0"
- "From\0Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>\0"
+ "From\0Kishon Vijay Abraham I <kishon@ti.com>\0"
  "Subject\0Re: [PATCH v5 2/2] phy: add a driver for the Rockchip SoC internal PCIe PHY\0"
  "Date\0Thu, 1 Sep 2016 10:35:16 +0530\0"
- "To\0Heiko St\303\274bner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>"
- " Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0"
- "Cc\0devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
-  Wenrui Li <wenrui.li-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
-  Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
-  linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
-  Doug Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
-  linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
- " Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>\0"
+ "To\0Heiko St\303\274bner <heiko@sntech.de>"
+ " Shawn Lin <shawn.lin@rock-chips.com>\0"
+ "Cc\0<linux-kernel@vger.kernel.org>"
+  <linux-rockchip@lists.infradead.org>
+  Doug Anderson <dianders@chromium.org>
+  Brian Norris <briannorris@chromium.org>
+  Wenrui Li <wenrui.li@rock-chips.com>
+  Rob Herring <robh+dt@kernel.org>
+ " <devicetree@vger.kernel.org>\0"
  "\00:1\0"
  "b\0"
  "\n"
@@ -25,7 +25,7 @@
  ">> Access the PHY via registers provided by GRF (general register\n"
  ">> files) module.\n"
  ">>\n"
- ">> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n"
+ ">> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>\n"
  "> \n"
  "> seems I'm late to the party, but when looking if I can apply the pcie-\n"
  "> devicetree patches, I found that the phy is still pending.\n"
@@ -94,4 +94,4 @@
  "> Heiko\n"
  >
 
-4c83b99ddc2c4114217231aab1d9e04f5e3ccb7e94afe9e2c0541c9408cea23b
+2fa02c13f6718886363a6c11b3ea5795bc6f316fd36922595f4624963bf77acc

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.