From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc Date: Fri, 02 Sep 2016 17:53:40 +0900 Message-ID: <57C93E14.5090500@samsung.com> References: <1472769085-20715-1-git-send-email-hl@rock-chips.com> <1472769085-20715-4-git-send-email-hl@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-path: In-reply-to: <1472769085-20715-4-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Lin Huang , heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org Cc: myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org, airlied-cv59FeDIM0c@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, tixy-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, typ-TNX95d0MmH7DzftRWevZcw@public.gmane.org, sudeep.holla-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-pm@vger.kernel.org On 2016년 09월 02일 07:31, Lin Huang wrote: > This patch adds the documentation for rockchip rk3399 dmc driver. > > Signed-off-by: Lin Huang > --- > Changes in v8: > - add ddr timing properties > > Changes in v7: > -None > > Changes in v6: > -Add more detail in Documentation > > Changes in v5: > -None > > Changes in v4: > -None > > Changes in v3: > -None > > Changes in v2: > -None > > Changes in v1: > -None > > .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 +++++++++++++++++++++ > 1 file changed, 173 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > > diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > new file mode 100644 > index 0000000..1f39b5cb > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > @@ -0,0 +1,173 @@ > +* Rockchip rk3399 DMC(Dynamic Memory Controller) device > + > +Required properties: > +- compatible: Must be "rockchip,rk3399-dmc". > +- devfreq-events: Node to get DDR loading, Refer to > + Documentation/devicetree/bindings/devfreq/ > + rockchip-dfi.txt > +- interrupts: The interrupt number to the CPU. The interrupt > + specifier format depends on the interrupt controller. > + It should be DCF interrupts, when DDR dvfs finish, > + it will happen. > +- clocks: Phandles for clock specified in "clock-names" property > +- clock-names : The name of clock used by the DFI, must be > + "pclk_ddr_mon"; > +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt > + for details. > +- center-supply: DMC supply node. > +- status: Marks the node enabled/disabled. > + > +Following properties are ddr timing: > + > +- dram_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h, > + it select ddr3 cl-trp-trcd type, default value > + "DDR3_DEFAULT".it must selected according to > + "Speed Bin" in ddr3 datasheet, DO NOT use smaller > + "Speed Bin" than ddr3 exactly is. > + > +- pd_idle : Config the PD_IDLE value, defined the power-down idle > + period, memories are places into power-down mode if > + bus is idle for PD_IDLE DFI clocks. > + > +- sr_idle : Configure the SR_IDLE value, defined the selfrefresh > + idle period, memories are places into self-refresh > + mode if bus is idle for SR_IDLE*1024 DFI clocks > + (DFI clocks freq is half of dram's clocks), defaule > + value is "0". > + > +- sr_mc_gate_idle : Defined the self-refresh with memory and controller > + clock gating idle period, memories are places into > + self-refresh mode and memory controller clock arg > + gating if bus is idle for sr_mc_gate_idle*1024 DFI > + clocks. > + > +- srpd_lite_idle : Defined the self-refresh power down idle period, > + memories are places into self-refresh power down > + mode if bus is idle for srpd_lite_idle*1024 DFI > + clocks. This parameter is for LPDDR4 only. > + > +- standby_idle : Defined the standby idle period, memories are places > + into self-refresh than controller, pi, phy and dram > + clock will gating if bus is idle for > + standby_idle * DFI clocks. > + > +- dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in MHz > + when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 > + dll will bypssed note: if dll was bypassed, the > + odt also stop working. > + > +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz), > + when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll > + will bypssed. note: phy dll and phy odt are > + independent > + > +- ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt > + on dram side and controller side are both disabled. > + > +- ddr3_drv : When dram type is DDR3, this parameter define the > + dram side driver stength in ohm, default value is > + DDR3_DS_40ohm. > + > +- ddr3_odt : When dram type is DDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + DDR3_ODT_120ohm. > + > +- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy > + side CA line(incluing command line, address line and > + clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_ddr3_dq_drv : When dram type is DDR3, this parameter define the phy > + side DQ line(incluing DQS/DQ/DM line) driver strength. > + default value is PHY_DRV_ODT_40. > + > +- phy_ddr3_odt : When dram type is DDR3, this parameter define the > + phy side odt strength, default value is > + PHY_DRV_ODT_240. > + > +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr3_drv : When dram type is LPDDR3, this parameter define the > + dram side driver stength in ohm, default value is > + LP3_DS_34ohm. > + > +- lpddr3_odt : When dram type is LPDDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + LP3_ODT_240ohm. > + > +- phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define the > + phy side CA line(incluing command line, address line > + and clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr3_odt : When dram type is LPDDR3, this parameter define the phy > + side odt strength, default value is PHY_DRV_ODT_240. > + > +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr4_drv : When dram type is LPDDR4, this parameter define the > + dram side driver stength in ohm, default value is > + LP4_PDDS_60ohm. > + > +- lpddr4_dq_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on dqs/dq line stength in ohm, default > + value is LP4_DQ_ODT_40ohm. > + > +- lpddr4_ca_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on ca line stength in ohm, default value > + is LP4_CA_ODT_40ohm. > + > +- phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define the > + phy side CA line(incluing command address line) > + driver strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the > + phy side clock line and cs line driver strength. > + default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_odt : When dram type is LPDDR4, this parameter define the > + phy side odt strength, default value is PHY_DRV_ODT_60. It is good to explain the each field for ddr timing. But, why you you drop the example for ddr timing values? I think that you better to add the example for ddr timing values > + > +Example: > + dmc_opp_table: dmc_opp_table { > + compatible = "operating-points-v2"; > + > + opp00 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <900000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <666000000>; > + opp-microvolt = <900000>; > + }; > + }; > + > + dmc: dmc { > + compatible = "rockchip,rk3399-dmc"; > + devfreq-events = <&dfi>; > + interrupts = ; > + clocks = <&cru SCLK_DDRCLK>; > + clock-names = "dmc_clk"; > + operating-points-v2 = <&dmc_opp_table>; > + center-supply = <&ppvar_centerlogic>; > + upthreshold = <15>; > + downdifferential = <10>; > + status = "disabled"; > + }; > + > -- Best Regards, Chanwoo Choi -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: cw00.choi@samsung.com (Chanwoo Choi) Date: Fri, 02 Sep 2016 17:53:40 +0900 Subject: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc In-Reply-To: <1472769085-20715-4-git-send-email-hl@rock-chips.com> References: <1472769085-20715-1-git-send-email-hl@rock-chips.com> <1472769085-20715-4-git-send-email-hl@rock-chips.com> Message-ID: <57C93E14.5090500@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 2016? 09? 02? 07:31, Lin Huang wrote: > This patch adds the documentation for rockchip rk3399 dmc driver. > > Signed-off-by: Lin Huang > --- > Changes in v8: > - add ddr timing properties > > Changes in v7: > -None > > Changes in v6: > -Add more detail in Documentation > > Changes in v5: > -None > > Changes in v4: > -None > > Changes in v3: > -None > > Changes in v2: > -None > > Changes in v1: > -None > > .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 +++++++++++++++++++++ > 1 file changed, 173 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > > diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > new file mode 100644 > index 0000000..1f39b5cb > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > @@ -0,0 +1,173 @@ > +* Rockchip rk3399 DMC(Dynamic Memory Controller) device > + > +Required properties: > +- compatible: Must be "rockchip,rk3399-dmc". > +- devfreq-events: Node to get DDR loading, Refer to > + Documentation/devicetree/bindings/devfreq/ > + rockchip-dfi.txt > +- interrupts: The interrupt number to the CPU. The interrupt > + specifier format depends on the interrupt controller. > + It should be DCF interrupts, when DDR dvfs finish, > + it will happen. > +- clocks: Phandles for clock specified in "clock-names" property > +- clock-names : The name of clock used by the DFI, must be > + "pclk_ddr_mon"; > +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt > + for details. > +- center-supply: DMC supply node. > +- status: Marks the node enabled/disabled. > + > +Following properties are ddr timing: > + > +- dram_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h, > + it select ddr3 cl-trp-trcd type, default value > + "DDR3_DEFAULT".it must selected according to > + "Speed Bin" in ddr3 datasheet, DO NOT use smaller > + "Speed Bin" than ddr3 exactly is. > + > +- pd_idle : Config the PD_IDLE value, defined the power-down idle > + period, memories are places into power-down mode if > + bus is idle for PD_IDLE DFI clocks. > + > +- sr_idle : Configure the SR_IDLE value, defined the selfrefresh > + idle period, memories are places into self-refresh > + mode if bus is idle for SR_IDLE*1024 DFI clocks > + (DFI clocks freq is half of dram's clocks), defaule > + value is "0". > + > +- sr_mc_gate_idle : Defined the self-refresh with memory and controller > + clock gating idle period, memories are places into > + self-refresh mode and memory controller clock arg > + gating if bus is idle for sr_mc_gate_idle*1024 DFI > + clocks. > + > +- srpd_lite_idle : Defined the self-refresh power down idle period, > + memories are places into self-refresh power down > + mode if bus is idle for srpd_lite_idle*1024 DFI > + clocks. This parameter is for LPDDR4 only. > + > +- standby_idle : Defined the standby idle period, memories are places > + into self-refresh than controller, pi, phy and dram > + clock will gating if bus is idle for > + standby_idle * DFI clocks. > + > +- dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in MHz > + when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 > + dll will bypssed note: if dll was bypassed, the > + odt also stop working. > + > +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz), > + when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll > + will bypssed. note: phy dll and phy odt are > + independent > + > +- ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt > + on dram side and controller side are both disabled. > + > +- ddr3_drv : When dram type is DDR3, this parameter define the > + dram side driver stength in ohm, default value is > + DDR3_DS_40ohm. > + > +- ddr3_odt : When dram type is DDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + DDR3_ODT_120ohm. > + > +- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy > + side CA line(incluing command line, address line and > + clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_ddr3_dq_drv : When dram type is DDR3, this parameter define the phy > + side DQ line(incluing DQS/DQ/DM line) driver strength. > + default value is PHY_DRV_ODT_40. > + > +- phy_ddr3_odt : When dram type is DDR3, this parameter define the > + phy side odt strength, default value is > + PHY_DRV_ODT_240. > + > +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr3_drv : When dram type is LPDDR3, this parameter define the > + dram side driver stength in ohm, default value is > + LP3_DS_34ohm. > + > +- lpddr3_odt : When dram type is LPDDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + LP3_ODT_240ohm. > + > +- phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define the > + phy side CA line(incluing command line, address line > + and clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr3_odt : When dram type is LPDDR3, this parameter define the phy > + side odt strength, default value is PHY_DRV_ODT_240. > + > +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr4_drv : When dram type is LPDDR4, this parameter define the > + dram side driver stength in ohm, default value is > + LP4_PDDS_60ohm. > + > +- lpddr4_dq_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on dqs/dq line stength in ohm, default > + value is LP4_DQ_ODT_40ohm. > + > +- lpddr4_ca_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on ca line stength in ohm, default value > + is LP4_CA_ODT_40ohm. > + > +- phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define the > + phy side CA line(incluing command address line) > + driver strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the > + phy side clock line and cs line driver strength. > + default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_odt : When dram type is LPDDR4, this parameter define the > + phy side odt strength, default value is PHY_DRV_ODT_60. It is good to explain the each field for ddr timing. But, why you you drop the example for ddr timing values? I think that you better to add the example for ddr timing values > + > +Example: > + dmc_opp_table: dmc_opp_table { > + compatible = "operating-points-v2"; > + > + opp00 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <900000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <666000000>; > + opp-microvolt = <900000>; > + }; > + }; > + > + dmc: dmc { > + compatible = "rockchip,rk3399-dmc"; > + devfreq-events = <&dfi>; > + interrupts = ; > + clocks = <&cru SCLK_DDRCLK>; > + clock-names = "dmc_clk"; > + operating-points-v2 = <&dmc_opp_table>; > + center-supply = <&ppvar_centerlogic>; > + upthreshold = <15>; > + downdifferential = <10>; > + status = "disabled"; > + }; > + > -- Best Regards, Chanwoo Choi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752735AbcIBIyS (ORCPT ); Fri, 2 Sep 2016 04:54:18 -0400 Received: from mailout4.samsung.com ([203.254.224.34]:57241 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752206AbcIBIyP (ORCPT ); Fri, 2 Sep 2016 04:54:15 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee68e-f79cb6d000006cfe-61-57c93e1504af Content-transfer-encoding: 8BIT Message-id: <57C93E14.5090500@samsung.com> Date: Fri, 02 Sep 2016 17:53:40 +0900 From: Chanwoo Choi Organization: Samsung Electronics User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Lin Huang , heiko@sntech.de Cc: myungjoo.ham@samsung.com, mark.yao@rock-chips.com, airlied@linux.ie, mturquette@baylibre.com, dbasehore@chromium.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, linux-arm-kernel@lists.infradead.org, tixy@linaro.org, typ@rock-chips.com, sudeep.holla@arm.com, mark.rutland@arm.com, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 3/5] Documentation: bindings: add dt documentation for rk3399 dmc References: <1472769085-20715-1-git-send-email-hl@rock-chips.com> <1472769085-20715-4-git-send-email-hl@rock-chips.com> In-reply-to: <1472769085-20715-4-git-send-email-hl@rock-chips.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjleLIzCtJLcpLzFFi42JZI2JSqCtqdzLcYNJ2GYvecyeZLF5t3sNm Mf/IOVaLs8sOsllc+fqezeL/o9esFj82nGK2ONv0ht1i0+NrrBaXd81hs/jce4TR4tOD/8wW S69fZLLYMeUAk8XFU64WtxtXsFn8ONPNYrH81A4Wi4Xz77NbzF5d5yDisWbeGkaP9zda2T1m N1xk8bjc18vkcefaHjaP7d8esHrc7z7O5LF5Sb3H31n7WTz6tqxi9Nh+bR6zx+dNcgE8UVw2 Kak5mWWpRfp2CVwZx48vYyrocarYNHEiUwPjE6MuRk4OCQETiX09a9kgbDGJC/fWA9lcHEIC KxglDm5fz97FyAFWtGJFOUR8FqPEm8PtrCANvAKCEj8m32MBqWEWkJc4cikbJMwsoC4xad4i Zoj6B4wSi28fZwKp4RXQkmg/6A5SwyKgKvGotZ0JxGYDCu9/cQPsBn4BRYmrPx4zgpSLCkRI dJ+oBAmLCBhJnP0ynwlkJLPAHWaJ2Tf2M4IkhAXCJa68Oc4Osesso8Sapt1gt3EKOEl0XzjM ApKQEPjBIfHo8kZmiM0CEt8mH2KBeExWYtMBZojnJSUOrrjBMoFRfBaS12YhvDYLyWsLGJlX MYqmFiQXFCelFxnpFSfmFpfmpesl5+duYgQmk9P/nvXtYLx5wPoQowAHoxIP7wWdk+FCrIll xZW5hxhNgY6YyCwlmpwPTFl5JfGGxmZGFqYmpsZG5pZmSuK8CVI/g4UE0hNLUrNTUwtSi+KL SnNSiw8xMnFwSjUwFtoXlt9bxPOwxnR6jccl9jfRLZf+vP20R8RzpULj8dZpdcXZemviA102 /Q98WDpj91QHL9kDlqcidJp0cxZlH3Ffy+6w5IlF/Af/3hBd0SeNpz4mG225e65T/aaRSmuw dlJuyTvniCnNlX9/1nesPzHzXOkxC++YfddM8n+35gnPeZRh0TJXiaU4I9FQi7moOBEAimwT CSEDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNKsWRmVeSWpSXmKPExsVy+t9jQV1Ru5PhBq/mCFv0njvJZPFq8x42 i/lHzrFanF12kM3iytf3bBb/H71mtfix4RSzxdmmN+wWmx5fY7W4vGsOm8Xn3iOMFp8e/Ge2 WHr9IpPFjikHmCwunnK1uN24gs3ix5luFovlp3awWCycf5/dYvbqOgcRjzXz1jB6vL/Ryu4x u+Eii8flvl4mjzvX9rB5bP/2gNXjfvdxJo/NS+o9/s7az+LRt2UVo8f2a/OYPT5vkgvgiWpg tMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLxCdB1y8wBelRJoSwx pxQoFJBYXKykb4dpQmiIm64FTGOErm9IEFyPkQEaSFjDmHH8+DKmgh6nik0TJzI1MD4x6mLk 4JAQMJFYsaK8i5ETyBSTuHBvPVsXIxeHkMAsRok3h9tZQRK8AoISPybfYwGpZxaQlzhyKRsk zCygLjFp3iJmiPoHjBKLbx9nAqnhFdCSaD/oDlLDIqAq8ai1nQnEZgMK739xgw3E5hdQlLj6 4zEjSLmoQIRE94lKkLCIgJHE2S/zmUBGMgvcYZaYfWM/I0hCWCBc4sqb4+wQu84ySqxp2g12 G6eAk0T3hcMsExgFZyE5dRbCqbOQnLqAkXkVo0RqQXJBcVJ6rmFearlecWJucWleul5yfu4m RnDCeia1g/HgLvdDjAIcjEo8vA+sToYLsSaWFVfmHmKU4GBWEuF1sAEK8aYkVlalFuXHF5Xm pBYfYjQFenYis5Rocj4wmeaVxBsam5gZWRqZG1oYGZsrifM+/r8uTEggPbEkNTs1tSC1CKaP iYNTqoFxyQSvl2fevpJgF939qfr2Hev4eGPW6zL7C5d33xI0n8I5mzc+RO587hLnlqdyO3g/ Tk502pv4oGk1L+eObLmmJ31Tnp1ITMg+cmqhe/PsfDur4wXPr97MX3pT8Zv49rW6rROzFP4e 2qG56bfc9Qyjh603Gb93yntHPu4OfWJz6cTciBN2ZpcWK7EUZyQaajEXFScCAHDgpApuAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2016년 09월 02일 07:31, Lin Huang wrote: > This patch adds the documentation for rockchip rk3399 dmc driver. > > Signed-off-by: Lin Huang > --- > Changes in v8: > - add ddr timing properties > > Changes in v7: > -None > > Changes in v6: > -Add more detail in Documentation > > Changes in v5: > -None > > Changes in v4: > -None > > Changes in v3: > -None > > Changes in v2: > -None > > Changes in v1: > -None > > .../devicetree/bindings/devfreq/rk3399_dmc.txt | 173 +++++++++++++++++++++ > 1 file changed, 173 insertions(+) > create mode 100644 Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > > diff --git a/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > new file mode 100644 > index 0000000..1f39b5cb > --- /dev/null > +++ b/Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt > @@ -0,0 +1,173 @@ > +* Rockchip rk3399 DMC(Dynamic Memory Controller) device > + > +Required properties: > +- compatible: Must be "rockchip,rk3399-dmc". > +- devfreq-events: Node to get DDR loading, Refer to > + Documentation/devicetree/bindings/devfreq/ > + rockchip-dfi.txt > +- interrupts: The interrupt number to the CPU. The interrupt > + specifier format depends on the interrupt controller. > + It should be DCF interrupts, when DDR dvfs finish, > + it will happen. > +- clocks: Phandles for clock specified in "clock-names" property > +- clock-names : The name of clock used by the DFI, must be > + "pclk_ddr_mon"; > +- operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt > + for details. > +- center-supply: DMC supply node. > +- status: Marks the node enabled/disabled. > + > +Following properties are ddr timing: > + > +- dram_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h, > + it select ddr3 cl-trp-trcd type, default value > + "DDR3_DEFAULT".it must selected according to > + "Speed Bin" in ddr3 datasheet, DO NOT use smaller > + "Speed Bin" than ddr3 exactly is. > + > +- pd_idle : Config the PD_IDLE value, defined the power-down idle > + period, memories are places into power-down mode if > + bus is idle for PD_IDLE DFI clocks. > + > +- sr_idle : Configure the SR_IDLE value, defined the selfrefresh > + idle period, memories are places into self-refresh > + mode if bus is idle for SR_IDLE*1024 DFI clocks > + (DFI clocks freq is half of dram's clocks), defaule > + value is "0". > + > +- sr_mc_gate_idle : Defined the self-refresh with memory and controller > + clock gating idle period, memories are places into > + self-refresh mode and memory controller clock arg > + gating if bus is idle for sr_mc_gate_idle*1024 DFI > + clocks. > + > +- srpd_lite_idle : Defined the self-refresh power down idle period, > + memories are places into self-refresh power down > + mode if bus is idle for srpd_lite_idle*1024 DFI > + clocks. This parameter is for LPDDR4 only. > + > +- standby_idle : Defined the standby idle period, memories are places > + into self-refresh than controller, pi, phy and dram > + clock will gating if bus is idle for > + standby_idle * DFI clocks. > + > +- dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in MHz > + when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 > + dll will bypssed note: if dll was bypassed, the > + odt also stop working. > + > +- phy_dll_disb_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz), > + when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll > + will bypssed. note: phy dll and phy odt are > + independent > + > +- ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt > + on dram side and controller side are both disabled. > + > +- ddr3_drv : When dram type is DDR3, this parameter define the > + dram side driver stength in ohm, default value is > + DDR3_DS_40ohm. > + > +- ddr3_odt : When dram type is DDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + DDR3_ODT_120ohm. > + > +- phy_ddr3_ca_drv : When dram type is DDR3, this parameter define the phy > + side CA line(incluing command line, address line and > + clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_ddr3_dq_drv : When dram type is DDR3, this parameter define the phy > + side DQ line(incluing DQS/DQ/DM line) driver strength. > + default value is PHY_DRV_ODT_40. > + > +- phy_ddr3_odt : When dram type is DDR3, this parameter define the > + phy side odt strength, default value is > + PHY_DRV_ODT_240. > + > +- lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined then > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr3_drv : When dram type is LPDDR3, this parameter define the > + dram side driver stength in ohm, default value is > + LP3_DS_34ohm. > + > +- lpddr3_odt : When dram type is LPDDR3, this parameter define the > + dram side ODT stength in ohm, default value is > + LP3_ODT_240ohm. > + > +- phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define the > + phy side CA line(incluing command line, address line > + and clock line) driver strength. default value is > + PHY_DRV_ODT_40. > + > +- phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr3_odt : When dram type is LPDDR3, this parameter define the phy > + side odt strength, default value is PHY_DRV_ODT_240. > + > +- lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter defined the > + odt disable frequency in MHz (Mega Hz), when ddr > + frequency less then ddr3_odt_disb_freq, the odt on > + dram side and controller side are both disabled. > + > +- lpddr4_drv : When dram type is LPDDR4, this parameter define the > + dram side driver stength in ohm, default value is > + LP4_PDDS_60ohm. > + > +- lpddr4_dq_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on dqs/dq line stength in ohm, default > + value is LP4_DQ_ODT_40ohm. > + > +- lpddr4_ca_odt : When dram type is LPDDR4, this parameter define the > + dram side ODT on ca line stength in ohm, default value > + is LP4_CA_ODT_40ohm. > + > +- phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define the > + phy side CA line(incluing command address line) > + driver strength. default value is PHY_DRV_ODT_40. > + > +- phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define the > + phy side clock line and cs line driver strength. > + default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define the > + phy side DQ line(incluing DQS/DQ/DM line) driver > + strength. default value is PHY_DRV_ODT_80. > + > +- phy_lpddr4_odt : When dram type is LPDDR4, this parameter define the > + phy side odt strength, default value is PHY_DRV_ODT_60. It is good to explain the each field for ddr timing. But, why you you drop the example for ddr timing values? I think that you better to add the example for ddr timing values > + > +Example: > + dmc_opp_table: dmc_opp_table { > + compatible = "operating-points-v2"; > + > + opp00 { > + opp-hz = /bits/ 64 <300000000>; > + opp-microvolt = <900000>; > + }; > + opp01 { > + opp-hz = /bits/ 64 <666000000>; > + opp-microvolt = <900000>; > + }; > + }; > + > + dmc: dmc { > + compatible = "rockchip,rk3399-dmc"; > + devfreq-events = <&dfi>; > + interrupts = ; > + clocks = <&cru SCLK_DDRCLK>; > + clock-names = "dmc_clk"; > + operating-points-v2 = <&dmc_opp_table>; > + center-supply = <&ppvar_centerlogic>; > + upthreshold = <15>; > + downdifferential = <10>; > + status = "disabled"; > + }; > + > -- Best Regards, Chanwoo Choi