diff for duplicates of <57C93F3E.4030802@samsung.com>

diff --git a/a/1.txt b/N1/1.txt
index 66f90df..6b4f48c 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,4 +1,4 @@
-On 2016=EB=85=84 08=EC=9B=94 28=EC=9D=BC 01:33, Krzysztof Kozlowski wrote:
+On 2016년 08월 28일 01:33, Krzysztof Kozlowski wrote:
 > On Thu, Aug 25, 2016 at 03:57:18PM +0900, Chanwoo Choi wrote:
 >> This patch sets the clock rate for DREX (DRAM Express) block
 >> on exynos5422-odroidxu3 board. In the exynos5422 TRM,
@@ -7,11 +7,11 @@ On 2016=EB=85=84 08=EC=9B=94 28=EC=9D=BC 01:33, Krzysztof Kozlowski wrote:
 >>
 > 
 >>From the commit message I don't get two things:
-> 1. Why setting this on XU3-family of boards, not all 542x/5800=3F
+> 1. Why setting this on XU3-family of boards, not all 542x/5800?
 
 I have the only xu3 board. I cannot test it on other boards.
 
-> 2. Why this is needed=3F The commit msg lacks the answer to the "why".
+> 2. Why this is needed? The commit msg lacks the answer to the "why".
 
 In the exynos5422's TRM, CMU_CDREX generates the 800MHz DRAM clock
 as above commit message. But, I'm missing what there is different
@@ -27,8 +27,8 @@ clock rate for DRAM on below.
 >>           dout_sclk_cdrex              0            0   800000000          0 0
 >>
 > 
-> What is the purpose of this dump of clk_summary=3F Is it a state before or
-> after the change=3F After it is quite obvious that it should have
+> What is the purpose of this dump of clk_summary? Is it a state before or
+> after the change? After it is quite obvious that it should have
 > 800MHz...
 
 I'm missing the difference before applying this patch.
@@ -69,16 +69,16 @@ Chanwoo Choi
 >> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
 >> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
 >> @@ -229,6 +229,11 @@
->>  	status =3D "okay";
+>>  	status = "okay";
 >>  };
 >>  
 >> +&clock {
->> +	assigned-clocks =3D <&clock CLK_DOUT_SCLK_CDREX>;
->> +	assigned-clock-rates =3D <800000000>;
+>> +	assigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>;
+>> +	assigned-clock-rates = <800000000>;
 >> +};
 >> +
 >>  &clock_audss {
->>  	assigned-clocks =3D <&clock_audss EXYNOS_MOUT_AUDSS>,
+>>  	assigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,
 >>  			<&clock_audss EXYNOS_MOUT_I2S>,
 >> -- 
 >> 1.9.1
diff --git a/a/content_digest b/N1/content_digest
index df3c1d9..fa7be1c 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -19,7 +19,7 @@
  " linux-arm-kernel@lists.infradead.org\0"
  "\00:1\0"
  "b\0"
- "On 2016=EB=85=84 08=EC=9B=94 28=EC=9D=BC 01:33, Krzysztof Kozlowski wrote:\n"
+ "On 2016\353\205\204 08\354\233\224 28\354\235\274 01:33, Krzysztof Kozlowski wrote:\n"
  "> On Thu, Aug 25, 2016 at 03:57:18PM +0900, Chanwoo Choi wrote:\n"
  ">> This patch sets the clock rate for DREX (DRAM Express) block\n"
  ">> on exynos5422-odroidxu3 board. In the exynos5422 TRM,\n"
@@ -28,11 +28,11 @@
  ">>\n"
  "> \n"
  ">>From the commit message I don't get two things:\n"
- "> 1. Why setting this on XU3-family of boards, not all 542x/5800=3F\n"
+ "> 1. Why setting this on XU3-family of boards, not all 542x/5800?\n"
  "\n"
  "I have the only xu3 board. I cannot test it on other boards.\n"
  "\n"
- "> 2. Why this is needed=3F The commit msg lacks the answer to the \"why\".\n"
+ "> 2. Why this is needed? The commit msg lacks the answer to the \"why\".\n"
  "\n"
  "In the exynos5422's TRM, CMU_CDREX generates the 800MHz DRAM clock\n"
  "as above commit message. But, I'm missing what there is different\n"
@@ -48,8 +48,8 @@
  ">>           dout_sclk_cdrex              0            0   800000000          0 0\n"
  ">>\n"
  "> \n"
- "> What is the purpose of this dump of clk_summary=3F Is it a state before or\n"
- "> after the change=3F After it is quite obvious that it should have\n"
+ "> What is the purpose of this dump of clk_summary? Is it a state before or\n"
+ "> after the change? After it is quite obvious that it should have\n"
  "> 800MHz...\n"
  "\n"
  "I'm missing the difference before applying this patch.\n"
@@ -90,16 +90,16 @@
  ">> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi\n"
  ">> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi\n"
  ">> @@ -229,6 +229,11 @@\n"
- ">>  \tstatus =3D \"okay\";\n"
+ ">>  \tstatus = \"okay\";\n"
  ">>  };\n"
  ">>  \n"
  ">> +&clock {\n"
- ">> +\tassigned-clocks =3D <&clock CLK_DOUT_SCLK_CDREX>;\n"
- ">> +\tassigned-clock-rates =3D <800000000>;\n"
+ ">> +\tassigned-clocks = <&clock CLK_DOUT_SCLK_CDREX>;\n"
+ ">> +\tassigned-clock-rates = <800000000>;\n"
  ">> +};\n"
  ">> +\n"
  ">>  &clock_audss {\n"
- ">>  \tassigned-clocks =3D <&clock_audss EXYNOS_MOUT_AUDSS>,\n"
+ ">>  \tassigned-clocks = <&clock_audss EXYNOS_MOUT_AUDSS>,\n"
  ">>  \t\t\t<&clock_audss EXYNOS_MOUT_I2S>,\n"
  ">> -- \n"
  ">> 1.9.1\n"
@@ -117,4 +117,4 @@
  "> \n"
  >
 
-3a3bae0cbc677850246fc6f4f8032c13eefe52a0cf0a83cc04b616ee7c6bf0ce
+f70e16825dadc45ab2887aecad9415fcea0ec594dc1f6f7838e3dd6784b47ec0
