From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailout4.samsung.com ([203.254.224.34]:45901 "EHLO mailout4.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751093AbcIGEa7 (ORCPT ); Wed, 7 Sep 2016 00:30:59 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 Message-id: <57CF9801.3080107@samsung.com> Date: Wed, 07 Sep 2016 13:30:57 +0900 From: Chanwoo Choi To: Sylwester Nawrocki , linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org Subject: Re: [PATCH v2 2/7] clk: samsung: exynos5410: Expose the peripheral DMA gate clocks References: <1473163496-17820-1-git-send-email-s.nawrocki@samsung.com> <1473163496-17820-3-git-send-email-s.nawrocki@samsung.com> In-reply-to: <1473163496-17820-3-git-send-email-s.nawrocki@samsung.com> Sender: linux-clk-owner@vger.kernel.org List-ID: On 2016년 09월 06일 21:04, Sylwester Nawrocki wrote: > These clocks are needed in order to use the PL330 peripheral > DMA controllers. > > Signed-off-by: Sylwester Nawrocki > Reviewed-by: Krzysztof Kozlowski > --- > drivers/clk/samsung/clk-exynos5410.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c > index 54ec486..cf6fb41 100644 > --- a/drivers/clk/samsung/clk-exynos5410.c > +++ b/drivers/clk/samsung/clk-exynos5410.c > @@ -176,6 +176,8 @@ static const struct samsung_gate_clock exynos5410_gate_clks[] __initconst = { > GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0), > GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0), > GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0), > + GATE(CLK_PDMA1, "pdma1", "aclk200", GATE_BUS_FSYS0, 2, 0, 0), > + GATE(CLK_PDMA0, "pdma0", "aclk200", GATE_BUS_FSYS0, 1, 0, 0), > > GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301", > GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0), Looks good to me. Reviewed-by: Chanwoo Choi -- Best Regards, Chanwoo Choi