diff for duplicates of <57D1664D.3060502@arm.com> diff --git a/a/1.txt b/N1/1.txt index 9182cb4..59faef9 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ -On 05/09/16 11:01, shh.xie at gmail.com wrote: -> From: Mingkai Hu <Mingkai.Hu@nxp.com> +On 05/09/16 11:01, shh.xie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote: +> From: Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org> > > LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks > are similar to LS1043A which also complies to Freescale Chassis 2.1 @@ -8,14 +8,14 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > Created LS1046A SoC DTSI file to be included by board level DTS > files. > -> Signed-off-by: Horia Geant? <horia.geanta@nxp.com> -> Signed-off-by: Mihai Bantea <mihai.bantea@nxp.com> -> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> -> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> -> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> -> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> -> Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com> -> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> +> Signed-off-by: Horia Geant? <horia.geanta-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Mihai Bantea <mihai.bantea-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Chenhui Zhao <chenhui.zhao-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Gong Qianyu <Qianyu.Gong-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Minghuan Lian <Minghuan.Lian-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org> +> Signed-off-by: Shaohui Xie <Shaohui.Xie-3arQi8VN3Tc@public.gmane.org> > --- > Changes in V2: > 1. addressed Arnd's comments. @@ -45,7 +45,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + * > + * Copyright 2016, Freescale Semiconductor, Inc. > + * -> + * Mingkai Hu <mingkai.hu@nxp.com> +> + * Mingkai Hu <mingkai.hu-3arQi8VN3Tc@public.gmane.org> > + * > + * This file is dual-licensed: you can use it either under the terms > + * of the GPLv2 or the X11 license, at your option. Note that this dual @@ -102,7 +102,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x0>; @@ -111,7 +111,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x1>; @@ -120,7 +120,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x2>; @@ -129,7 +129,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x3>; @@ -156,7 +156,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + }; > + @@ -201,7 +201,7 @@ Please add "arm,cortex-a72-pmu". > + <&cpu3>; > + }; > + -> + gic: interrupt-controller at 1400000 { +> + gic: interrupt-controller@1400000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; @@ -221,3 +221,7 @@ Thanks, M. -- Jazz is not dead. It just smells funny... +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 15e7be7..07e01e1 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,13 +1,31 @@ "ref\01473069695-33092-1-git-send-email-shh.xie@gmail.com\0" "ref\01473069695-33092-4-git-send-email-shh.xie@gmail.com\0" - "From\0marc.zyngier@arm.com (Marc Zyngier)\0" - "Subject\0[PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support\0" + "ref\01473069695-33092-4-git-send-email-shh.xie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org\0" + "From\0Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>\0" + "Subject\0Re: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support\0" "Date\0Thu, 8 Sep 2016 14:23:25 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0shh.xie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" + devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + catalin.marinas-5wv7dgnIgG8@public.gmane.org + will.deacon-5wv7dgnIgG8@public.gmane.org + shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + " linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0Mihai Bantea <mihai.bantea-3arQi8VN3Tc@public.gmane.org>" + Chenhui Zhao <chenhui.zhao-3arQi8VN3Tc@public.gmane.org> + arnd-r2nGTMty4D4@public.gmane.org + Shaohui Xie <Shaohui.Xie-3arQi8VN3Tc@public.gmane.org> + Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org> + Minghuan Lian <Minghuan.Lian-3arQi8VN3Tc@public.gmane.org> + Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org> + Horia Geant? <horia.geanta-3arQi8VN3Tc@public.gmane.org> + " Gong Qianyu <Qianyu.Gong-3arQi8VN3Tc@public.gmane.org>\0" "\00:1\0" "b\0" - "On 05/09/16 11:01, shh.xie at gmail.com wrote:\n" - "> From: Mingkai Hu <Mingkai.Hu@nxp.com>\n" + "On 05/09/16 11:01, shh.xie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org wrote:\n" + "> From: Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org>\n" "> \n" "> LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks\n" "> are similar to LS1043A which also complies to Freescale Chassis 2.1\n" @@ -16,14 +34,14 @@ "> Created LS1046A SoC DTSI file to be included by board level DTS\n" "> files.\n" "> \n" - "> Signed-off-by: Horia Geant? <horia.geanta@nxp.com>\n" - "> Signed-off-by: Mihai Bantea <mihai.bantea@nxp.com>\n" - "> Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com>\n" - "> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>\n" - "> Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>\n" - "> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>\n" - "> Signed-off-by: Mingkai Hu <Mingkai.Hu@nxp.com>\n" - "> Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>\n" + "> Signed-off-by: Horia Geant? <horia.geanta-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Mihai Bantea <mihai.bantea-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Chenhui Zhao <chenhui.zhao-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Gong Qianyu <Qianyu.Gong-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Minghuan Lian <Minghuan.Lian-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Mingkai Hu <Mingkai.Hu-3arQi8VN3Tc@public.gmane.org>\n" + "> Signed-off-by: Shaohui Xie <Shaohui.Xie-3arQi8VN3Tc@public.gmane.org>\n" "> ---\n" "> Changes in V2:\n" "> 1. addressed Arnd's comments.\n" @@ -53,7 +71,7 @@ "> + *\n" "> + * Copyright 2016, Freescale Semiconductor, Inc.\n" "> + *\n" - "> + * Mingkai Hu <mingkai.hu@nxp.com>\n" + "> + * Mingkai Hu <mingkai.hu-3arQi8VN3Tc@public.gmane.org>\n" "> + *\n" "> + * This file is dual-licensed: you can use it either under the terms\n" "> + * of the GPLv2 or the X11 license, at your option. Note that this dual\n" @@ -110,7 +128,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x0>;\n" @@ -119,7 +137,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x1>;\n" @@ -128,7 +146,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x2>;\n" @@ -137,7 +155,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x3>;\n" @@ -164,7 +182,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t};\n" "> +\n" @@ -209,7 +227,7 @@ "> +\t\t\t\t <&cpu3>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 1400000 {\n" + "> +\tgic: interrupt-controller@1400000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\tinterrupt-controller;\n" @@ -228,6 +246,10 @@ "\n" "\tM.\n" "-- \n" - Jazz is not dead. It just smells funny... + "Jazz is not dead. It just smells funny...\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -161ece2c3efe4bdb07a3dafd911874e40474a6e2d62a2e5d41402f4c2e30792c +a9cc42d8c2b44432a688f6eb5ac03066a663ad400abda2a879968683d550961f
diff --git a/a/1.txt b/N2/1.txt index 9182cb4..3cbf067 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,4 +1,4 @@ -On 05/09/16 11:01, shh.xie at gmail.com wrote: +On 05/09/16 11:01, shh.xie@gmail.com wrote: > From: Mingkai Hu <Mingkai.Hu@nxp.com> > > LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks @@ -102,7 +102,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + #address-cells = <1>; > + #size-cells = <0>; > + -> + cpu0: cpu at 0 { +> + cpu0: cpu@0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x0>; @@ -111,7 +111,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu1: cpu at 1 { +> + cpu1: cpu@1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x1>; @@ -120,7 +120,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu2: cpu at 2 { +> + cpu2: cpu@2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x2>; @@ -129,7 +129,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + cpu-idle-states = <&CPU_PH20>; > + }; > + -> + cpu3: cpu at 3 { +> + cpu3: cpu@3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72"; > + reg = <0x3>; @@ -156,7 +156,7 @@ On 05/09/16 11:01, shh.xie at gmail.com wrote: > + }; > + }; > + -> + memory at 80000000 { +> + memory@80000000 { > + device_type = "memory"; > + }; > + @@ -201,7 +201,7 @@ Please add "arm,cortex-a72-pmu". > + <&cpu3>; > + }; > + -> + gic: interrupt-controller at 1400000 { +> + gic: interrupt-controller@1400000 { > + compatible = "arm,gic-400"; > + #interrupt-cells = <3>; > + interrupt-controller; diff --git a/a/content_digest b/N2/content_digest index 15e7be7..68deaba 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,12 +1,29 @@ "ref\01473069695-33092-1-git-send-email-shh.xie@gmail.com\0" "ref\01473069695-33092-4-git-send-email-shh.xie@gmail.com\0" - "From\0marc.zyngier@arm.com (Marc Zyngier)\0" - "Subject\0[PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support\0" + "From\0Marc Zyngier <marc.zyngier@arm.com>\0" + "Subject\0Re: [PATCH 3/7] [v2] arm64: dts: add QorIQ LS1046A SoC support\0" "Date\0Thu, 8 Sep 2016 14:23:25 +0100\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0shh.xie@gmail.com" + devicetree@vger.kernel.org + robh+dt@kernel.org + mark.rutland@arm.com + linux-arm-kernel@lists.infradead.org + catalin.marinas@arm.com + will.deacon@arm.com + shawnguo@kernel.org + " linux-kernel@vger.kernel.org\0" + "Cc\0Mihai Bantea <mihai.bantea@nxp.com>" + Chenhui Zhao <chenhui.zhao@nxp.com> + arnd@arndb.de + Shaohui Xie <Shaohui.Xie@nxp.com> + Hou Zhiqiang <Zhiqiang.Hou@nxp.com> + Minghuan Lian <Minghuan.Lian@nxp.com> + Mingkai Hu <Mingkai.Hu@nxp.com> + Horia Geant? <horia.geanta@nxp.com> + " Gong Qianyu <Qianyu.Gong@nxp.com>\0" "\00:1\0" "b\0" - "On 05/09/16 11:01, shh.xie at gmail.com wrote:\n" + "On 05/09/16 11:01, shh.xie@gmail.com wrote:\n" "> From: Mingkai Hu <Mingkai.Hu@nxp.com>\n" "> \n" "> LS1046A is an SoC with 4 ARMv8 A72 cores and most other IP blocks\n" @@ -110,7 +127,7 @@ "> +\t\t#address-cells = <1>;\n" "> +\t\t#size-cells = <0>;\n" "> +\n" - "> +\t\tcpu0: cpu at 0 {\n" + "> +\t\tcpu0: cpu@0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x0>;\n" @@ -119,7 +136,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu at 1 {\n" + "> +\t\tcpu1: cpu@1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x1>;\n" @@ -128,7 +145,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu at 2 {\n" + "> +\t\tcpu2: cpu@2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x2>;\n" @@ -137,7 +154,7 @@ "> +\t\t\tcpu-idle-states = <&CPU_PH20>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu at 3 {\n" + "> +\t\tcpu3: cpu@3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\";\n" "> +\t\t\treg = <0x3>;\n" @@ -164,7 +181,7 @@ "> +\t\t};\n" "> +\t};\n" "> +\n" - "> +\tmemory at 80000000 {\n" + "> +\tmemory@80000000 {\n" "> +\t\tdevice_type = \"memory\";\n" "> +\t};\n" "> +\n" @@ -209,7 +226,7 @@ "> +\t\t\t\t <&cpu3>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller at 1400000 {\n" + "> +\tgic: interrupt-controller@1400000 {\n" "> +\t\tcompatible = \"arm,gic-400\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\tinterrupt-controller;\n" @@ -230,4 +247,4 @@ "-- \n" Jazz is not dead. It just smells funny... -161ece2c3efe4bdb07a3dafd911874e40474a6e2d62a2e5d41402f4c2e30792c +ad431e6603eca722af2dc3dcf637b62f84c9ecff5e2b5b626d2f41b51f16b0a9
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